ALD500AU/ALD500A/ALD500

Advanced Linear Devices

7

ALD500AU/ALD500A/ALD500 CONVERSION CYCLE

The ALD500AU/ALD500A/ALD500 conversion cycle takes

place in four distinct phases, the Auto Zero Phase, the Input

Signal Integration Phase, the Reference Voltage Deintegration

Phase, and the Integrator Zero Phase. A typical measurement

cycle uses all four phases in an order sequence as mentioned

above. The internal analog switch status for each of these

phases is summarized in Table 1.

The following is a detailed description of each one of the four

phases of the conversion cycle.

Auto Zero Phase (AZ Phase)

The analog-to-digital conversion cycle begins with the Auto

Zero Phase, when the digital controller applies low logic level

to input A and high logic level to input B of the analog

processor. During this phase, the reference voltage is stored

the sum of the buffer and integrator offset voltages are stored

comparator output is characterized by an indeterminate

waveform.

During the Auto Zero Phase, the external input signal is

disconnected from the internal circuitry of the ALD500AU/

and connecting the internal input nodes internally to analog

ground. A feedback loop, closed around the integrator and

compensate for buffer amplifier, integrator and comparator

offset voltages.

This is the system initialization phase, when a conversion is

ready to be initiated at system turn-on.

In practice the

converter can be operated in continuous conversion mode,

where AZ phase must be long enough for the circuit conditions

to settle out any system errors. Typically this phase is set to

Input Signal Integration Phase (INT Phase)

During the Input Signal Integration Phase (INT), the ALD500AU/

ALD500A/ALD500 integrates the differential voltage across

within the device's common-mode voltage range CMVR. The

fixed number of clock pulses, at a rate determined by the

magnitude of the input voltage. During this phase, the analog

inputs see only the high impedance of the noninverting

operational amplifier input of the buffer. The integrator responds

only to the voltage difference between the analog input

terminals, thus providing true differential analog inputs.

The input signal polarity is determined by software control at

sign bit for the overall conversion result.

The duration of this phase is selected by design to be a fixed

time and depends on system parameters and component

value selections. The total number of clock pulses or clock

counts, during integration phase determine the resolution of

the conversion. For high resolution applications, this total

number of clock pulses should be maximized. The basic unit

of resolution is in

µV/count. Before the end of this phase,

comparator output is sampled by the microcontroller. This

phase is terminated by changing logic inputs AB from 10 to 11.

At the end of the Input Signal Integration Phase, Reference

Voltage Deintegration Phase begins. The previously charged

reference capacitor is connected with the proper polarity to

ramp the integrator output back to zero. The ALD500AU/

ALD500A/ALD500 analog processors automatically selects

the proper logic state to cause the integrator to ramp back

toward zero at a rate proportional to the reference voltage

stored on the reference capacitor. The time required to return

to zero is measured by the counter in the digital processor

using the same crystal oscillator. The phase is terminated by

the comparator output after the comparator senses when the

integrator output crosses zero. The counter contents are then

transferred to the register. The resulting time measurement

is proportional to the magnitude of the applied input voltage.

The duration of this phase is precisely measured from the

transition of AB from 10 to 11 to the falling edge of the

comparator output, usually with a crystal controlled digital

counter chain. The comparator delay contributes some error

in this phase. The typical comparator delay is 1

comparator delay and overshoot will result in error timing,

which translates into error voltages. This error can be zeroed

and minimized during Integrator Output Zero Phase and

corrected in software, to within

±1 count of the crystal clock

(which is equivalent to within

± 1 LSB, when 1 clock pulse = 1

LSB).

This phase guarantees the integrator output is at 0V when the

Auto Zero phase is entered, and that only system offset

voltages are compensated. This phase is used at the end of

the reference voltage deintegration and is used for applications

with high resolutions. If this phase is not used, the value of the

of charge-sharing.

The Integrator Zero phase should be

programmed to operate until the Output of the Comparator

returns "HIGH". A typical Integrator Zero Phase lasts 1msec.

The comparator delay and the controller's response latency

may result in Overshoot causing charge buildup on the

integrator at the end of a conversion. This charge must be

removed or performance will degrade. The Integrator Output

high. At this point, the integrator output is near zero. Auto Zero

Phase should be entered (AB = 01) and the ALD500AU/

ALD500A/ALD500 is held in this state until the next conversion

cycle.