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ALD500R Datasheet(PDF) 2 Page - Advanced Linear Devices |
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ALD500R Datasheet(HTML) 2 Page - Advanced Linear Devices |
2 / 12 page 2 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R GENERAL THEORY OF OPERATION Dual-Slope Conversion Principles of Operation The basic principle of dual-slope integrating analog to digital converter is simple and straightforward. A capacitor, CINT, is charged with the integrator from a starting voltage, VX, for a fixed period of time at a rate determined by the value of an unknown input voltage, which is the subject of measurement. Then the capacitor is discharged at a fixed rate, based on an external reference voltage, back to VX where the discharge time, or deintegration time, is measured precisely. Both the integration time and deintegration time are measured by a digital counter controlled by a crystal oscillator. It can be demonstrated that the unknown input voltage is determined by the ratio of the deintegration time and integration time, and is directly proportional to the magnitude of the external reference voltage. The major advantages of a dual-slope converter are: a. Accuracy is not dependent on absolute values of integration time tINT and deintegration time tDINT, but is dependent on their relative ratios. Long-term clock frequency variations will not affect the accuracy. A standard crystal controlled clock running digital counters is adequate to generate very high accuracies. b. Accuracy is not dependent on the absolute values of RINT and CINT, as long as the component values do not vary through a conversion cycle, which typically lasts less than 1 second. c. Offset voltage values of the analog components, such as VX, are cancelled out and do not affect accuracy. d. Accuracy of the system depends mainly on the accuracy and the stability of the voltage reference value. FIGURE 1. ALD500R Functional Block Diagram GENERAL DESCRIPTION The ALD500RAU/ALD500RA/ALD500R are integrating dual slope analog processors, designed to operate on ±5V power supplies for building precision analog-to-digital converters. The ALD500RAU/ALD500RA/ALD500R feature specifications suitable for 18 bit/17 bit/16 bit resolution conversion, respectively. Together with three capacitors, two resistors, and a digital controller, a precision Analog to Digital converter with auto zero can be implemented. The digital controller can be implemented by an external microcontroller, under either hardware (fixed logic) or software control. For ultra high resolution applications, up to 23 bit conversion can be implemented with an appropriate digital controller and software. The ALD500R series of analog processors accept differential inputs and the external digital controller first counts the number of pulses at a fixed clock rate that a capacitor requires to integrate against an unknown analog input voltage, then counts the number of pulses required to deintegrate the capacitor against a known internal reference voltage. This unknown analog voltage can then be converted by the microcontroller to a digital word, which is translated into a high resolution number, representing an accurate reading. This reading, when ratioed against the reference voltage, yields an accurate, absolute voltage measurement reading. The ALD500R analog processors consist of on-chip digital control circuitry to accept control inputs, integrating buffer amplifiers, analog switches, and voltage comparators and a highly accurate, ultra-stable voltage reference. It functions in four operating modes, or phases, namely auto zero, integrate, deintegrate, and integrator zero phases. At the end of a conversion, the comparator output goes from high to low when the integrator crosses zero during deintegration. ALD500R analog processors also provide direct logic interface to CMOS logic families. SW-R N/C - + - + + - + - (2) (17) (18) COUT DGND Level Shift Polarity Detection Phase Decoding Logic Comp2 Comp1 Integrator Buffer REF Control Bias Analog Switch Control Signals Control Logic CS A B AGND (13) (6) (14) (8) (12) (11) (7) (5) (3) (19) (10) (9) (1) (16) (15) (20) IB N/C VDD VSS CINT CINT RINT CAZ CAZ C-REF SWAZ SWS SWR SWR CREF SWAz SWIN SWG SWIN C+REF V+REF V-REF SW-R SW+R SW+R V-IN V+IN BUF REFINT (4) RREF = 100KΩ CB = 0.1µF RREF CB |
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