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ALD500A Datasheet(PDF) 2 Page - Advanced Linear Devices |
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ALD500A Datasheet(HTML) 2 Page - Advanced Linear Devices |
2 / 11 page 2 Advanced Linear Devices ALD500AU/ALD500A/ALD500 GENERAL THEORY OF OPERATION Dual-Slope Conversion Principles of Operation The basic principle of dual-slope integrating analog to digital converter is simple and straightforward. A capacitor, CINT, is charged with the integrator from a starting voltage, VX, for a fixed period of time at a rate determined by the value of an unknown input voltage, which is the subject of measurement. Then the capacitor is discharged at a fixed rate, based on an external reference voltage, back to VX where the discharge time, or deintegration time, is measured precisely. Both the integration time and deintegration time are measured by a digital counter controlled by a crystal oscillator. It can be demonstrated that the unknown input voltage is determined by the ratio of the deintegration time and integration time, and is directly proportional to the magnitude of the external reference voltage. The major advantages of a dual-slope converter are: a. Accuracy is not dependent on absolute values of integration time tINT and deintegration time tDINT, but is dependent on their relative ratios. Long-term clock frequency variations will not affect the accuracy. A standard crystal controlled clock running digital counters is adequate to generate very high accuracies. b. Accuracy is not dependent on the absolute values of RINT and CINT. as long as the component values do not vary through a conversion cycle, which typically lasts less than 1 second. c. Offset voltage values of the analog components, such as VX, are cancelled out and do not affect accuracy. d. Accuracy of the system depends mainly on the accuracy and the stability of the voltage reference value. e. Very high resolution, high accuracy measurements can be achieved simply and at very low cost. An inherent benefit of the dual slope converter system is noise immunity. The input noise spikes are integrated (averaged to near zero) during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters and other high resolution converters and perform very well in high-noise environments. The slow conversion speed of the integrating converter provides inherent noise rejection with at least a 20dB/decade attenuation rate. Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed. Integrating converters often establish the integration period to reject 50/60Hz line frequency interference signals. The relationship of the integrate and deintegrate (charge and discharge) of the integrating capacitor values are shown below: VINT = VX - (VIN . tINT / RINT . CINT) FIGURE 1. ALD 500 Functional Block Diagram SW-R - + - + + - + - (1) (14) (15) COUT DGND Level Shift Polarity Detection Phase Decoding Logic Comp2 Comp1 Integrator Buffer Analog Switch Control Signals Control Logic A B AGND (10) (5) (11) (7) (9) (8) (6) (4) (2) (16) (13) (12) VDD VSS CINT CINT RINT CAZ CAZ C-REF SWAZ SWS SWR SWR CREF SWAz SWIN SWG SWIN C+REF V+REF V-REF SW-R SW+R SW+R V-IN V+IN BUF (3) |
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