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SE370C722FZT Datasheet(PDF) 11 Page - Texas Instruments

Part # SE370C722FZT
Description  8-BIT MICROCONTROLLER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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SE370C722FZT Datasheet(HTML) 11 Page - Texas Instruments

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TMS370Cx2x
8-BIT MICROCONTROLLER
SPNS018C – FEBRUARY 1993 – REVISED FEBRUARY 1997
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
program EPROM
The TMS370C722 and SE370C722 devices contain 8K bytes of program EPROM mapped, beginning at
location 6000h and continuing through location 7FFFh, as shown in Figure 3. Reading the program EPROM
modules is identical to reading other internal memory. During programming, the program EPROM is controlled
by the EPROM control register (EPCTL). The program EPROM module features include:
D Programming
In-circuit programming capability if VPP is applied to MC
Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in
the peripheral file (PF) frame at location P01C as shown in Table 5.
D Write protection: Writes to the program EPROM are disabled under the following conditions:
Reset: All programming to the EPROM module is halted
Low-power modes
13 V not applied to MC
program ROM
The program ROM consists of 4K or 8K bytes of mask programmable read-only memory (see Table 6). The
program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is
performed at the time of device fabrication.
Table 6. Program ROM Memory Map
’x20A
’x22A
ROM size
4K bytes
8K bytes
Memory mapped
7000h – 7FFFh
6000h – 7FFFh
system reset
The system-reset operation ensures an orderly start-up sequence for the TMS370Cx2x CPU-based device.
Three actions can cause a system reset. Two of these actions are internally generated, while one (RESET) is
controlled externally. These actions are as follows:
D Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key
register, or if the re-initialization does not occur before the watchdog timer timeout . See the
TMS370 Family
User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number
SPNS014B) for more information.
D Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See
the
TMS370 Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual
(literature number SPNS014B) for more information.
D External RESET Pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the
TMS370 Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature
number SPNS014B) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x2x device to reset external system components. Additionally, if a cold start (VCC is off
for several hundred milliseconds) condition or oscillator failure occurs or RESET pin is held low, then the reset
logic holds the device in a reset state for as long as these actions are active.
† Memory addresses 7FF0h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15
instructions are located between addresses 7FC0h and 7FDFh.


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