TLV2543C, TLV2543I

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS096C – MARCH 1995 – REVISED JUNE 2000

7

POST OFFICE BOX 655303

EOC output

The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During

the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high

until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs

after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input

data register. After the EOC signal goes low, the analog input signal can be changed without affecting the

conversion result.

The EOC signal goes high again after the conversion completes and the conversion result is latched into the

output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.

On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When

CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the

falling edge of CS.

data format and pad bits

D3 and D2 of the input data register determine the number of significant bits in the digital output that represent

the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines

the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.

The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of

the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are

transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion

result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are

zeros.

When CS is held low continuously, the first data bit of the just completed conversion occurs on DATA OUT on

the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes

low and the serial output is forced to a logic zero until EOC goes high again.

When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS.

On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next

bit in the serial conversion result until the required number of bits has been output.

chip-select input (CS)

The chip-select input (CS) enables and disables the device. During normal operation, CS should be low.

Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between

conversions to coordinate the data transfer of several devices sharing the same bus.

When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing

its output data line to other devices that may share it. After an internally generated debounce time, the I/O

CLOCK is inhibited, thus preventing any further change in the internal state.

When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce

time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)

for a minimum time before a new I/O cycle can start.

CS can be used to interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low

long enough before the end of the current conversion cycle, the previous conversion result is saved in the

internal output buffer and then shifted out during the next I/O cycle.