TLV2543C, TLV2543I

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS096C – MARCH 1995 – REVISED JUNE 2000

8

POST OFFICE BOX 655303

power-down features

When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles,

the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse.

During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed,

and the internal output buffer keeps the previous conversion cycle data results, provided that all digital inputs

completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,

the converter normally begins in the power-down mode. The device remains in the power-down mode until a

valid (other than 1110) input address clocks in. Upon completion of that I/O cycle, a normal conversion is

performed with the results being shifted out during the next I/O cycle.

analog input, test, and power-down mode

The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer

according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type

to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on

the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held

on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer,

sampled, and converted in the same manner as the external analog inputs. The first conversion after the device

has returned from the power-down state may not read accurately due to internal device settling.

Table 2. Analog-Channel-Select Address

ANALOG INPUT

SELECTED

VALUE SHIFTED INTO

DATA INPUT

SELECTED

BINARY

HEX

AIN0

0000

0

AIN1

0001

1

AIN2

0010

2

AIN3

0011

3

AIN4

0100

4

AIN5

0101

5

AIN6

0110

6

AIN7

0111

7

AIN8

1000

8

AIN9

1001

9

AIN10

1010

A

Table 3. Test-Mode-Select Address

INTERNAL

SELF-TEST

VOLTAGE

VALUE SHIFTED INTO

DATA INPUT

UNIPOLAR OUTPUT

RESULT (HEX)‡

VOLTAGE

SELECTED†

BINARY

HEX

RESULT (HEX)‡

Vref + – Vref –

2

1011

B

200

Vref –

1100

C

000

Vref +

1101

D

3FF

† Vref+ is the voltage applied to REF+, and Vref– is the voltage applied to REF–.

‡ The output results shown are the ideal values and may vary with the reference stability

and with internal offsets.