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AKD5351 Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AKD5351 Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
8 / 19 page ASAHI KASEI [AK5351] 0166-E-00 1997/4 - 8 - SWITCHING CHARACTERISTICS (Ta=25 °C; VA,VD,VB=5.0V±10%; CL=20pF) Parameter Symbol min typ max Unit Control Clock Frequency Master Clock 256fs: Pulse width Low Pulse width High 384fs: Pulse width Low Pulse width High Serial Data Output Clock Channel Select Clock(Sampling Frequency) Duty Cycle fCLK tCLKL tCLKH fCLK tCLKL tCLKH fSLK fs 2.048 30.0 30.0 3.072 20.0 20.0 8 25 12.288 18.432 3.072 48 13.824 20.736 6.912 54 75 MHz ns ns MHz ns ns MHz kHz % Serial Interface Timing (Note 14 ) Slave Mode(SMODE1="L") SCLK Period SCLK Pulse width Low Pulse width High SCLK Rising to LRCK Edge (Note 15 ) LRCK Edge to SCLK Rising (Note 15 ) LRCK Edge to SDATA MSB Valid SCLK Falling to SDATA Valid SCLK Rising to FSYNC Edge(Note 15 ) FSYNC Edge to SCLK Rising(Note 15 ) Master Mode(SMODE1="H") SCLK Frequency Duty Cycle FSYNC Frequency Duty Cycle SCLK Falling to LRCK Edge LRCK Edge to FSYNC Rising SCLK Falling to SDATA Valid SCLK Falling to FSYNC Edge tSLK tSLKL tSLKH tSHLR tLRSH tDLR tDSS tSHF tFSH fSLK fFSYNC tSLR tLRF tDSS tSF 144.7 65 65 30 30 30 30 -20 -20 64fs 50 2fs 50 1 50 50 20 50 20 ns ns ns ns ns ns ns ns ns Hz % Hz % ns tslk ns ns Power down timing PD Pulse width PD Rising to SDATA Valid (Note 16 ) tPDW tPDV 150 516 ns 1/fs Note 14 : Refer to Serial Data Interface. Note 15 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK. Note 16 : The number of LRCK rising edges after PD brought high. The value is in master mode. In slave mode it becomes one LRCK clock(1/fs) longer. |
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