[ASAHI KASEI]

[AK4545]

MS0058-E-00

2000/11

- 7 -

Switching Characteristics

Ta=25°C, AVdd=5.0V±5%, DVdd=3.3V±5%, 50pF external load

Parameter

Symbol

Min

Typ

max

Units

Master Clock Frequency

Note)

If Crystal is not used.

Fmclk

-

45

24.576

50

-

55

MHz

%

AC link Interface Timing

BIT_CLK frequency

BIT_CLK clock Period(Tbclk=1/Fbclk)

BIT_BLK low pulse width

BIT_BLK low pulse width

BIT_CLK rise time

BIT_CLK fall time

Fbclk

Tbclk

Tclk_low

Tclk_high

Trise_clk

Tfall_clk

-

36

36

-

-

12.288

81.38

40.7

40.7

-

-

45

45

6

6

MHz

ns

ns

ns

ns

ns

SYNC frequency

SYNC low pulse width

SYNC high pulse width

SYNC rise time

SYNC fall time

Tsync_low

Tsync_high

Trise_sync

Tfall_sync

-

-

-

-

-

48

19.5

(240 cycle)

1.3

(16 cycle)

-

-

-

-

-

6

6

kHz

µs

(Tbclk)

µs

(Tbclk)

ns

ns

Setup time(SYNC, SDATA_OUT)

Hold time(SYNC, SDATA_OUT)

SDATA_IN delay time from BIT_CLK

rising edge

SDATA_IN rise time

SDATA_IN fall time

SDATA_OUT rise time

SDATA_OUT fall time

Tsetup

Thold

Tdelay

Trise_din

Tfall_din

Trise_dout

Tfall_dout

10

25

-

-

-

-

-

-

-

-

-

-

-

-

-

-

15

6

6

6

6

ns

ns

ns

ns

ns

ns

ns

Cold Rest (SDATA_OUT=L, SYNC=L)

RESET# active low pulse width

RESET# inactive to BIT_CLK delay

Trst_low

Trst2clk

1.0

162.8

(2 cycle)

--

µs

ns

(Tbclk)

Warm Rest Timing

SYNC active low pulse width

SYNC inactive to BIT_CLK delay

Tsync_high

Tsync2clk

1.0

162.8

(2 cycle)

1.3

(16 cycle)

-

µs

(Tbclk)

ns

(Tbclk)

AC-link Low Power Mode Timing

End of Slot 2 to BIT_CLK, SDATA_IN

Low

Ts2_pdwn

-

-

1.0

µs

Activate Test Mode Timing

Setup to trailing edge of RESET#

Hold from RESET# rising edge

Rising edge of RESET# to Hi-Z

Falling edge of RESET# to “L”

Tsetup2rst

Thold2rst

Toff

Tlow

15.0

100

-

-

-

-

-

-

-

-

50

50

ns

ns

ns

ns

Note ) The use of a crystal is recommended. If master clock is supplied from controller (or if a external oscillator is

used), Master Clock should be input to XTAL_IN, meanwhile XTAL_OUT should be open.