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AD9831ASTZ Datasheet(PDF) 3 Page - Analog Devices |
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AD9831ASTZ Datasheet(HTML) 3 Page - Analog Devices |
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3 / 16 page  AD9831 –3– TIMING CHARACTERISTICS (V DD = +3.3 V 10%, +5 V 10%; AGND = DGND = 0 V, unless otherwise noted) Limit at TMIN to TMAX Parameter (A Version) Units Test Conditions/Comments t1 40 ns min MCLK Period t2 16 ns min MCLK High Duration t3 16 ns min MCLK Low Duration t4* 8 ns min WR Rising Edge to MCLK Rising Edge t4A* 8 ns min WR Rising Edge After MCLK Rising Edge t5 8 ns min WR Pulse Width t6 t1 ns min Duration between Consecutive WR Pulses t7 5 ns min Data/Address Setup Time t8 3 ns min Data/Address Hold Time t9* 8 ns min FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge t9A* 8 ns min FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge t10 t1 ns min RESET Pulse Duration *See Pin Description section. Guaranteed by design but not production tested. t 1 t 4 MCLK WR t 2 t 3 t 4A t 6 t 5 Figure 2. Clock Synchronization Timing A0, A1, A2 DATA WR t 8 t 5 t 7 t 6 VALID DATA VALID DATA Figure 3. Parallel Timing VALID DATA VALID DATA VALID DATA MCLK FSELECT PSEL0, PSEL1 RESET t 9 t 10 t 9A Figure 4. Control Timing REV. B |
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