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AIC3842 Datasheet(PDF) 5 Page - Analog Intergrations Corporation |
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AIC3842 Datasheet(HTML) 5 Page - Analog Intergrations Corporation |
5 / 7 page AIC3842 5 n BLOCK DIAGRAM 8 6 R S VCC GND VREF 5V/50mA COMP OUTPUT VFB ISENSE RT/CT VREF Good Logic UVLO PWM Latch OSC ZD 34V Current Sense comparator Internal Bias Error Amp. D1 Z1 1V D2 R2 2.50V S/R 5V REF Q2 Q1 7 5 4 1 2 3 n PIN DESCRIPTIONS PIN 1: COMP - This pin is the error amplifier output and is made available for loop compensation. PIN 2: VFB - This is the inverting input of the error amplifier. It is normally connected to the switching power supply output through a resistor divider. PIN 3: ISENSE - A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. PIN 4: RT/CT - The oscillator frequency and maximum output duty cycle are programmed by connecting resistor RT to VREF and capacitor CT to ground. Operation to 500KHz is feasible. PIN 5: GND- This pin is the combined control circuitry and power ground. PIN 6: OUTPUT- This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. PIN 7: VCC - This pin is the positive supply of the control IC. PIN 8: VREF - This is the reference output. It provides charging current for capacitor CT through resistor RT. |
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