TPS796

www.ti.com

SLVS351O – SEPTEMBER 2002 – REVISED NOVEMBER 2013

THERMAL INFORMATION

DRB

DCQ

KTT

UNITS

8 PINS

6 PINS

5 PINS

47.8

70.4

25

83

70

35

N/A

N/A

N/A

°C/W

2.1

6.8

1.5

17.8

30.1

8.52

12.1

6.3

0.4

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.

(2)

For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3)

Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as

specified in the JESD51 series. The following assumptions are used in the simulations:

(a)

i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.

(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper

coverage.

coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To

understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature

sections of this data sheet.

(4)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(5)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(6)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(7)

The junction-to-top characterization parameter,

from the simulation data to obtain

(8)

The junction-to-board characterization parameter,

from the simulation data to obtain

(9)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Copyright © 2002–2013, Texas Instruments Incorporated

Submit Documentation Feedback

3