Copyright

© ANPEC Electronics Corp.

Rev. A.4 - Jan., 2013

www.anpec.com.tw

11

APA3160

Function Description

Clock And PLL

The APA3160 is a slave device and receives signals from MCLK, SCLK, and LRCLK. The digital audio processor

(DAP) provides all sample rates and MCLK rates which defined in the clock control register.

The APA3160 checks to verify that SCLK is a particular value of 32f

The timing relationship of these clocks to SDIN is shown in subsequent sections.

Serial Data Interface

Serial data is an input transmitted to SDIN. The PWM outputs are derived from SDIN. Besides, the APA3160 DAP

PWM Section

The APA3160 DAP device is a high power efficiency and high-performance digital audio reproduction. A noise shaper

is used to increase dynamic range and SNR in the audio band. The PWM section receives 24bit PCM data from the

DAP and outputs two BTL PWM audio output channels.

The PWM section has individual channel dc blocking filters that can be enabled and disabled. The low pass filter cutoff

frequency is less than 1Hz. Besides, the PWM section includes individual channel de-emphasis filters for 44.1 and 48

kHz and can be enabled and disabled.

The adjustable maximum modulation limit of PWM section is from 93.8% to 98.4%.

serial control interface supports both normal-speed 100kHz and high-speed 400kHz operations without waiting

states. As an added feature, even though the MCLK is absent, the interface operates.

For status registers, the serial control interface provides both single-byte and multi-byte read and write operations;

and for the general control registers, they associated with the PWM.