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SP3220EBEA-LTR Datasheet(PDF) 11 Page - Exar Corporation |
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SP3220EBEA-LTR Datasheet(HTML) 11 Page - Exar Corporation |
11 / 21 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com SP3220E_EB_EU_101_060311 11 Charge Pump The charge pump is an Exar-patended design (U.S. 5,306,954) and uses a unique approach compared to older less-efficient designs. The charge pump still requires four external capacitors, but uses a four-phase voltage shifting technique to attain sym- metrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages of +/-5.5V regardless of the input voltage (Vcc) over the +3.0V to +5.5V range. In most circumstances, decoupling the power supply can be achieved adequately using a 0.1µF bypass capacitor at C5 (refer to figures 6 and 7). In applications that are sensitive to power-supply noise, decouple Vcc to ground with a capacitor of the same value as charge-pump capacitor C1. Physi- cally connect bypass capcitors as close to the IC as possible. The charge pump operates in a discontinu- ous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the outputvoltages exceedamagnitudeof5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shift- ing. A description of each phase follows. Phase 1 — V SS charge storage — During this phase of the clock cycle, the positive side of capaci- tors C 1 and C2 are initially charged to VCC. C l + is then switched to GND and the charge in C 1 – is transferred to C 2 – . Since C 2 + is con- nected to V CC, the voltage potential across capacitor C 2 is now 2 times VCC. Phase 2 — V SS transfer — Phase two of the clock connectsthenegativeterminalofC 2 to the VSS storagecapacitorandthepositiveterminalof C 2 to GND. This transfers a negative gener- ated voltage to C 3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the volt- age to C 3, the positive side of capacitor C1 is switched to V CC and the negative side is connected to GND. Phase 3 — V DD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C 1 produces –VCC in the negative terminal of C 1, which is applied to the negative side of capacitor C 2. Since C 2 + is at V CC, the voltage potential across C2 is 2 times V CC. Phase 4 — V DD transfer — The fourth phase of the clock connects the negative terminal of C 2 to GND, and transfers this positive generated voltage across C 2 to C4, the V DD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the in- ternal oscillator is disabled. Simultaneous with the transfer of the voltage to C 4, the positive side of capacitor C 1 is switched to V CC and the negative side is con- nected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V– are separately gener- ated from V CC, in a no–load condition V + and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. DESCRIPTION |
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