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APW7057 Datasheet(PDF) 10 Page - Anpec Electronics Coropration

Part # APW7057
Description  High Power Step-Down Synchronous DC/DC Controller
Download  15 Pages
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Manufacturer  ANPEC [Anpec Electronics Coropration]
Direct Link  http://www.anpec.com.tw
Logo ANPEC - Anpec Electronics Coropration

APW7057 Datasheet(HTML) 10 Page - Anpec Electronics Coropration

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Copyright
© ANPEC Electronics Corp.
Rev. A.5 - Jun., 2008
APW7057
www.anpec.com.tw
10
Application Information
2
2
Component Selection Guidelines
Output Capacitor Selection
The selection of C
OUT is determined by the required effec-
tive series resistance (ESR) and voltage rating rather than
the actual capacitance requirement. Therefore, select high
performance low ESR capacitors that are intended for
switching regulator applications. In some applications,
multiple capacitors have to be paralled to achieve the
desired ESR value. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
current rating requirement is approximately I
OUT/2 , where
I
OUT is the load current. During power up, the input capaci-
tors have to handle large amount of surge current. If tanta-
lum capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
manufacturer.
For high frequency decoupling, a ceramic capacitor be-
tween 0.1
µF to 1µF can be connected between V
CC and
ground pin.
Inductor Selection
The inductance of the inductor is determined by the out-
put voltage requirement. The larger the inductance, the
lower the inductor’s current ripple. This will translate into
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
I
RIPPLE =
V
IN - VOUT
Fs x L
V
OUT
V
IN
x
∆V
OUT = IRIPPLE x ESR
where Fs is the switching frequency of the regulator.
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time. A
smaller inductor will give the regulator a faster load tran-
sient response at the expense of higher ripple current
and vice versa.
The maximum ripple current occurs at the maximum in-
put voltage. A good starting point is to choose the ripple
current to be approximately 30% of the maximum output
current.
Once the inductance value has been chosen, select an
inductor that is capable of carrying the required peak cur-
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
MOSFET Selection
The selection of the N-channel power MOSFETs are de-
termined by the R
DS(ON), reverse transfer capacitance (CRSS)
and maximum output current requirement.The losses in
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
losses are approximately given by the following equations:
P
UPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
P
LOWER = Iout (1+ TC)(RDS(ON))(1-D)
where I
OUT is the load current
TC is the temperature dependency of R
DS(ON)
F
S is the switching frequency
t
sw is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while
the upper MOSFET includes an additional transition loss.
The switching internal, t
sw, is the function of the reverse
transfer capacitance C
RSS. Figure 3 illustrates the switch-
ing waveform internal of the MOSFET.
Layout Consideration
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Signal
and power grounds are to be kept separate and finally
combined using ground plane construction or single point
grounding. Figure 4 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together.


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