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TMC2249AH6C2 Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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TMC2249AH6C2 Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 18 page TMC2249A PRODUCT SPECIFICATION REV. 1.0.2 7/6/00 3 Functional Description The TMC2249A performs the summation of products described by the formula: S(N+5) =A(N-ADEL) × B(N-BDEL) × (-1NEG1(N)) + C(N-CDEL) × D(N-DDEL) × (-1NEG2(N)) + CAS(N+3 × FT) where ADEL through DDEL range from 1 to 16 pipe delays. All inputs and controls utilize pipeline delay registers to maintain synchronicity with the data input during that clock, except when the Cascade data input is routed directly to the accumulator by use of the Feedthrough control. One-half LSB rounding to 16 bits may be performed on the sum of products while summing with the cascade input data. The user may access either the upper or lower 16 bits of the 24-bit accumulator by swapping overlapping registers. The output bus has an asynchronous high-impedance enable, to simplify interfacing to complex systems. Pin Assignments 120 Pin Metric Quad Flat Pack, KE Package CLK ACC NEG1 NEG2 RND S15 S14 GND S13 S12 S11 VDD S10 S9 S8 GND S7 S8 S5 VDD S4 S3 S2 GND S1 S0 OE SWAP BDEL0 BDEL1 1 30 120 91 31 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 61 BDEL2 BDEL3 ENB B0 B1 B2 B3 B4 B5 B6 B7 GND B8 B9 B10 VDD B11 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ENA 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name Pin Name ADEL3 ADEL2 ADEL1 ADEL0 NC CAS15 CAS14 CAS13 CAS12 CAS11 CAS10 GND CAS9 CAS8 CAS7 CAS6 CAS5 CAS4 CAS3 CAS2 CAS1 CAS0 CASEN FT CDEL0 CDEL1 CDEL2 CDEL3 ENC C0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 VDD D11 D10 D9 GND D8 D7 D6 D5 D4 D3 D2 D1 D0 END DDEL3 DDEL2 DDEL1 DDEL0 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name Pin Name |
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