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APL3526BBQBI-TRG Datasheet(PDF) 9 Page - Anpec Electronics Coropration |
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APL3526BBQBI-TRG Datasheet(HTML) 9 Page - Anpec Electronics Coropration |
9 / 14 page Copyright © ANPEC Electronics Corp. Rev. A.4 - Aug., 2013 www.anpec.com.tw 9 APL3526/B Application Information Recommended Minimum Footprint Layout Consideration The PCB layout should be carefully performed to maxi- mize thermal dissipation and to minimize voltage drop, droop and EMI. The following guidelines must be considered: 1. Please place the input capacitors near the VIN pin as close as possible. 2. Output decoupling capacitors for load must be placed near the load as close as possible for decoupling high frequency ripples. 3. Locate APL3526/B and output capacitors near the load to reduce parasitic resistance and inductance for excel- lent load transient performance. 4. The negative pins of the input and output capacitors and the GND pin must be connected to the ground plane of the load. 5. Keep VIN and VOUT traces as wide and short as possible. TDFN2x2-8 0.3 0.5 0.3 0.8 0.54 The via diameter = 0.305 Hole size = 0.203 Unit: mm Ground plane for Thermal PAD |
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