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TMC22071A Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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TMC22071A Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 24 page  TMC22071A PRODUCT SPECIFICATION 2 Functional Description The TMC22071A is a fully-integrated genlocking video A/D converter which digitizes NTSC or PAL baseband composite video under program control. It accepts video on three selectable input channels, adjusts gain, clamps to the back porch, and digitizes the video at a multiple of the horizontal line frequency. It extracts horizontal and vertical sync, mea- sures the subcarrier frequency and phase (relative to the sam- pling clock), and provides the data along with digital composite video data over an 8-bit digital video port. Two sync outputs (GHSYNC and GVSYNC) are also provided. It generates 1x (LDV) and 2x (PXCK) pixel clocks for data transfer. PXCK also serves as a master clock for the compan- ion TMC22x9x Encoders and TMC22x5y decoders. Operating parameters are set up via a serial microprocessor port. Internal or external voltage reference operation is avail- able Timing The TMC22071A operates from an internally-synthesized clock, PXCK, which runs at twice the pixel data rate. The nominal pixel rates may be set to 12.27 Mpps for NTSC and 13.5 Mpps for NTSC and PAL. Customers requiring 14.75 or 15 Mpps PAL operation should consult factory. Video Input Three high-impedance video inputs are selected by an inter- nal multiplexer under host processor control. The device accepts industry-standard video levels of 1.23 Volts (sync tip to peak color = 1 volt sync tip to reference white). Good channel-to-channel isolation allows active video on all three inputs simultaneously. Antialiasing filtering (if used) and line termination resistors must be provided externally. The input selection is controlled by two bits in the Control Regis- ter. Analog Clamp The front-end analog clamp ensures that the input video falls within the active range of the A/D converter. The digitized composite video output can be clamped to the back porch by a secondary digital clamp. Automatic Gain Adjustment Since video signals may vary substantially from nominal lev- els, the TMC22071A performs an automatic level setting routine to establish correct signal amplitudes for digitizing. The TMC22071A relies upon the presence of the sync tip-to-back porch voltage to determine the gain required for the input video signal. Sync tip compression or clipping is often affected by APL (Average Picture Level) variation. Rather than tracking minor variations in sync tip amplitude and constantly adjust- ing video gain, the TMC22071A establishes proper signal amplitudes during initial genlock acquisition, and then (optionally) holds the gain constant. This results in a stable picture under variable signal conditions. Improperly terminated or weak video signals are handled in the TMC22071A by a selectable gain of +1.0 or +1.5. The higher gain can amplify a doubly-terminated signal which is reduced in amplitude by 2/3. If the input signal levels are well controlled, the automatic gain adjustment can be disabled and the gain held at its nom- inal value (unity or 1.5X). Analog-to-Digital Converter The TMC22071A contains a high-performance 8-bit A/D converter. Its gain and offset are automatically set as a part of the automatic gain adjustment process during initial signal acquisition, and require no user attention. The reference voltages to the A/D converter are set up by internal D/A converters under automatic control during gen- lock acquisition. These voltages determine the gain and off- set of the A/D converter with respect to the video level presented at its input. Low-Pass Filter The digitized composite video stream is digitally low-pass filtered to remove chrominance components from the sync separator. Filtering provides robust operation by optimizing the signal-to-noise ratio of the synchronizing/blanking por- tion of the video, improving the accuracy of the back porch blanking level detector. A digital sync separator provides the output sync signals, GHSYNC and GVSYNC, and times internal operations. Horizontal Phase-Locked Loop A phase-locked loop generates PXCK, at twice the pixel rate. The reference signal for the horizontal phase-locked loop is generated by the Direct Digital Synthesizer (DDS). The DDS output is constructed with an internal D/A con- verter and is output from the TMC22071A via the DDS OUT pin. This signal is passed through an external LC filter and input to the horizontal phase-comparator. The frequency of the DDS output is one ninth of that of PXCK. A 20 MHz clock is required to drive the DDS. Preferably, this may be input to the TMC22071A via CMOS levels on the CLK IN pin. Alternately, a 20 MHz crystal may be directly connected between CLK IN and CLK OUT with tuning capacitors to activate the internal crystal oscillator cir- cuitry. If incoming video is lost or disconnected after the TMC22071A has acquired and locked, PXCK, GHSYNC, |
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