–5–

REV. B

AD7851

Descriptions that refer to SCLK

↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin

LOW, then the opposite edge of SCLK will apply.

Parameter

(A, K Versions)

Unit

Description

2

500

kHz min

Master Clock Frequency

7

MHz max

3

10

MHz max

Interface Modes 1, 2, 3 (External Serial Clock)

MHz max

Interface Modes 4, 5 (Internal Serial Clock)

4

100

ns min

CONVST Pulse Width

50

ns max

CONVST

↓ to BUSY↑ Propagation Delay

3.25

µs max

ns min

SYNC

↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)

ns min/max

SYNC

↓ to SCLK↓ Setup Time (Continuous SCLK Input)

ns min

SYNC

↓ to SCLK↓ Setup Time, Interface Mode 4 Only

5

30

ns max

Delay from

SYNC

↓ until DOUT Three-State Disabled

5

30

ns max

Delay from

SYNC

↓ until DIN Three-State Disabled

5

45

ns max

Data Access Time after SCLK

↓

30

ns min

Data Setup Time prior to SCLK

↑

20

ns min

Data Valid to SCLK Hold Time

6

ns min

SCLK High Pulse Width (Interface Modes 4 and 5)

6

ns min

SCLK Low Pulse Width (Interface Modes 4 and 5)

30

ns min

SCLK

↑ to SYNC↑ Hold Time (Noncontinuous SCLK)

ns min/max

(Continuous SCLK) Does Not Apply to Interface Mode 3

50

ns max

SCLK

↑ to SYNC↑ Hold Time

7

50

ns max

Delay from

SYNC

↑ until DOUT Three-State Enabled

90

ns max

Delay from SCLK

↑ to DIN Being Configured as Output

8

50

ns max

Delay from SCLK

↑ to DIN Being Configured as Input

ns max

CAL

↑ to BUSY↑ Delay

ns max

CONVST

↓ to BUSY↑ Delay in Calibration Sequence

9

41.7

ms typ

Full Self-Calibration Time, Master Clock Dependent

9

37.04

ms typ

Internal DAC Plus System Full-Scale Calibration Time, Master Clock

9

4.63

ms typ

System Offset Calibration Time, Master Clock Dependent

65

ns max

Delay from CLK to SCLK

NOTES

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

Table X and timing diagrams for different interface modes and calibration.

CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-

Down section).

relinquish time of the part and is independent of the bus loading.

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true

delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing

that a bus conflict will not occur.

Specifications subject to change without notice.