LPC11E37FBD64 datasheet(2/66 Pages) NXP

Part #	LPC11E37FBD64

Description	32-bit ARM Cortex-M0 microcontroller up to 128 kB flash up to 12 kB SRAM and 4 kB EEPROM USART

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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LPC11E3X

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Product data sheet

Rev. 2 — 21 November 2013

2 of 66

NXP Semiconductors

LPC11E3x

32-bit ARM Cortex-M0 microcontroller

 Debug options:

 Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan

Description Language).

 Serial Wire Debug.

 Digital peripherals:

 Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors, repeater mode, and open-drain mode.

 Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.

 Two GPIO grouped interrupt modules enable an interrupt based on a

programmable pattern of input states of a group of GPIO pins.

 High-current source output driver (20 mA) on one pin.

 High-current sink driver (20 mA) on true open-drain pins.

 Four general purpose counter/timers with a total of up to 8 capture inputs and 13

match outputs.

 Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal

low-power WatchDog Oscillator (WDO).

 Analog peripherals:

 10-bit ADC with input multiplexing among eight pins.

 Serial interfaces:

 USART with fractional baud rate generation, internal FIFO, a full modem control

handshake interface, and support for RS-485/9-bit mode and synchronous mode.

USART supports an asynchronous smart card interface (ISO 7816-3).

 Two SSP controllers with FIFO and multi-protocol capabilities.

 I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with

a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.

 I/O Handler for hardware emulation of serial interfaces and DMA; supported through

software libraries.(LPC11E37HFBD64/401 only.)

 Clock generation:

 Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).

 12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as

a system clock.

 Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable

frequency output.

 PLL allows CPU operation up to the maximum CPU rate with the system oscillator

or the IRC as clock sources.

 Clock output function with divider that can reflect the crystal oscillator, the main

clock, the IRC, or the watchdog oscillator.

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, Power-down, and Deep power-down modes.

 Power profiles residing in boot ROM provide optimized performance and minimized

power consumption for any given application through one simple function call.

 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

 Processor wake-up from Deep-sleep and Power-down modes via reset, selectable

GPIO pins, or the watchdog interrupt.

 Processor wake-up from Deep power-down mode using one special function pin.

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