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MPC8360ECVVAGFGA Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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MPC8360ECVVAGFGA Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 102 page  MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5 4 Freescale Semiconductor – 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a media-independent interface (MII, RMII, RGMII)1 – 1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2 – 9.6-Kbyte jumbo frames – ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in accordance ITU-T I.363.5 – ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2 – ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up to 64-Kbyte simultaneous ATM channels – ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000 – IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1) – ATM Transmission Convergence layer support in accordance with ITU-T I.432 – ATM OAM handling features compatible with ITU-T I.610 – PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs: 1661, 1662, 1990, 2686, and 3153 – IP support for IPv4 packets including TOS, TTL, and header checksum processing – Ethernet over first mile IEEE 802.3ah – Shim header – Ethernet-to-Ethernet/AAL5/AAL2 inter-working – L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags – ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM ports to Ethernet ports – Extensive support for ATM statistics and Ethernet RMON/MIB statistics – AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate – Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY – POS hardware; microcode must be loaded as an IRAM package – Transparent up to 70-Mbps full-duplex – HDLC up to 70-Mbps full-duplex – HDLC BUS up to 10 Mbps – Asynchronous HDLC –UART – BISYNC up to 2 Mbps – User-programmable Virtual FIFO size – QUICC multichannel controller (QMC) for 64 TDM channels — One multichannel communication controller (MCC) only on the MPC8360E supporting the following: – 256 HDLC or transparent channels – 128 SS7 channels – Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces — Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional 2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY — Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management 1.SMII or SGMII media-independent interface is not currently supported. |
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