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NSVB143TPDXV6T1G Datasheet(PDF) 1 Page - ON Semiconductor |
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NSVB143TPDXV6T1G Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 15 page © Semiconductor Components Industries, LLC, 2012 January, 2012 − Rev. 7 1 Publication Order Number: NSBC114EPDXV6/D NSBC114EPDXV6T1G, NSVBC114EPDXV6T1G Series Dual Bias Resistor Transistors NPN and PNP Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. In the NSBC114EPDXV6T1 series, two complementary BRT devices are housed in the SOT−563 package which is ideal for low power surface mount applications where board space is at a premium. Features • Simplifies Circuit Design • Reduces Board Space • Reduces Component Count • Available in 8 mm, 7 inch Tape and Reel • AEC−Q101 Qualified and PPAP Capable • NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements • These are Pb−Free Devices* MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1 and Q2, − minus sign for Q1 (PNP) omitted) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DEVICE MARKING INFORMATION See specific marking information in the device marking table on page 2 of this data sheet. Q1 R1 R2 R2 R1 Q2 (1) (2) (3) (4) (5) (6) http://onsemi.com SOT−563 CASE 463A PLASTIC xx = Specific Device Code (see table on page 2) M = Date Code G =Pb−Free Package MARKING DIAGRAM xx MG G Device Package Shipping† ORDERING INFORMATION NSBC114EPDXV6T1G SOT−563 4 mm pitch 4000/Tape & Reel NSBC114EPDXV6T5G SOT−563 2 mm pitch 8000/Tape & Reel (Note: Microdot may be in either location) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. |
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