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LT3431 Datasheet(PDF) 6 Page - Linear Technology |
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LT3431 Datasheet(HTML) 6 Page - Linear Technology |
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6 / 24 page  LT3844 6 3844fb PIN FUNCTIONS BURST_EN (Pin 4): The BURST_EN pin is used to enable or disable Burst Mode operation. Connect the BURST_EN pin to ground to enable the burst mode function. Connect the pin to VFB or VCC to disable the Burst Mode function. VFB (Pin 5): The output voltage feedback pin, VFB, is externally connected to the supply output voltage via a resistive divider. The VFB pin is internally connected to the inverting input of the error amplifier. In regulation, VFB is 1.231V. VC (Pin 6): The VC pin is the output of the error amplifier whose voltage corresponds to the maximum (peak) switch current per oscillator cycle. The error amplifier is typically configured as an integrator circuit by connecting an RC network from the VC pin to SGND. This circuit creates the dominant pole for the converter regulation control loop. Specific integrator characteristics can be configured to optimize transient response. When Burst Mode operation is enabled (see Pin 4 description), an internal low imped- ance clamp on the VC pin is set at 100mV below the burst threshold, which limits the negative excursion of the pin voltage. Therefore, this pin cannot be pulled low with a low impedance source. If the VC pin must be externally manipulated, do so through a 1k series resistance. SYNC (Pin 7): The SYNC pin provides an external clock input for synchronization of the internal oscillator. RSET is set such that the internal oscillator frequency is 10% to 25% below the external clock frequency. If unused the SYNC pin is connected to SGND. For more information see “Oscillator Sync” in the Applications Information section of this data sheet. fSET (Pin 8): The fSET pin programs the oscillator frequency with an external resistor, RSET. The resistor is required even when supplying external sync clock signal. See the Applications Information section for resistor value selec- tion details. SGND (Pin 9, 17): The SGND pin is the low noise ground reference. It should be connected to the –VOUT side of the output capacitors. Careful layout of the PCB is necessary to keep high currents away from this SGND connection. See the Applications Information section for helpful hints on PCB layout of grounds. SENSE– (Pin 10): The SENSE– pin is the negative input for the current sense amplifier and is connected to the VOUT side of the sense resistor for step-down applications. The sensed inductor current limit is set to 100mV across the SENSE inputs. SENSE+ (Pin 11): The SENSE+ pin is the positive input for the current sense amplifier and is connected to the induc- tor side of the sense resistor for step-down applications. The sensed inductor current limit is set to 100mV across the SENSE inputs. PGND (Pin 12): The PGND pin is the high current ground reference for internal low side switch and the VCC regulator circuit. Connect the pin directly to the negative terminal of the VCCdecouplingcapacitor.SeetheApplicationsInforma- tion section for helpful hints on PCB layout of grounds. VCC (Pin 13): The VCC pin is the internal bias supply decoupling node. Use a low ESR 1μF or greater ceramic capacitor to decouple this node to PGND. Most internal IC functions are powered from this bias supply. An external diode connected from VCC to the BOOST pin charges the bootstrapped capacitor during the off-time of the main power switch. Back driving the VCC pin from an external DC voltage source, such as the VOUT output of the regula- tor supply, increases overall efficiency and reduces power dissipation in the IC. In shutdown mode this pin sinks 20μA until the pin voltage is discharged to 0V. SW (Pin 14): In step-down applications the SW pin is connected to the cathode of an external clamping Schottky diode, the drain of the power MOSFET and the inductor. The SW node voltage swing is from VIN during the on- time of the power MOSFET, to a Schottky voltage drop below ground during the off-time of the power MOSFET. In start-up and in operating modes where there is insuf- ficient inductor current to freewheel the Schottky diode, an internal switch is turned on to pull the SW pin to ground so that the BOOST pin capacitor can be charged. Give careful consideration in choosing the Schottky diode to limit the negative voltage swing on the SW pin. TG (Pin 15): The TG pin is the bootstrapped gate drive for the top N-Channel MOSFET. Since very fast high currents are driven from this pin, connect it to the gate of the power MOSFET with a short and wide, typically 0.02" width, PCB trace to minimize inductance. |
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