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SPT7855SCT Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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SPT7855SCT Datasheet(HTML) 8 Page - Fairchild Semiconductor |
8 / 11 page 8 5/25/01 SPT7855 Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF – VRHS = 2.25 % of (VRHF – VRLF) (typical), and the bottom side voltage drop for VRLS to VRLF will equal: VRLS – VRLF = 1.9 % of (VRHF – VRLF) (typical). Figure 4 shows an example of expected voltage drops for a specific case. VREF of 4.0 V is applied to VRHF, and VRLF is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V), and a 75 mV increase is seen at VRLS (= 0.075 V). ANALOG INPUT VIN is the analog input. The input voltage range is from VRLS to VRHS (typically 4.0 V) and will scale proportionally with respect to the voltage reference. (See voltage refer- ence section.) The drive requirements for the analog inputs are very minimal when compared to most other converters due to the SPT7855’s extremely low input capacitance of only 5 pF and very high input resistance of 50 k Ω. The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. Upon powerup, the SPT7855 begins its calibration algo- rithm. In order to achieve the calibration accuracy re- quired, the offset and gain adjustment step size is a frac- tion of a 10-bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon powerup of 400 µsec (for a 25 MHz clock). Once calibrated, the SPT7855 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the SPT7855 to remain in calibration. INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit shown in figure 6. This circuit provides ESD robust- ness to 3.5 kV and prevents latch-up under severe dis- charge conditions without degrading analog transition times. Figure 5 – Recommended Input Protection Circuit 47 W D1 D2 ADC Buffer AVDD +V V D1 = D2 = Hewlett-Packard HP5712 or equivalent Figure 6 – On-Chip Protection Circuit VDD Analog Pad 120 W 120 W CALIBRATION The SPT7855 uses an auto-calibration scheme to ensure 10-bit accuracy over time and temperature. Gain and off- set errors are continually adjusted to 10-bit accuracy during device operation. This process is completely trans- parent to the user. POWER SUPPLY SEQUENCING CONSIDERATIONS All logic inputs should be held low until power to the device has settled to the specific tolerances. Avoid power decou- pling networks with large time constants that could delay VDD power to the device. CLOCK INPUT The SPT7855 is driven from a single-ended TTL-input clock. Because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance. |
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