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SPT7725BIQ Datasheet(PDF) 7 Page - Fairchild Semiconductor |
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SPT7725BIQ Datasheet(HTML) 7 Page - Fairchild Semiconductor |
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7 / 12 page  7 8/17/01 SPT7725 the same source. The SPT7725 is superior to similar de- vices, due to a preamplifier stage before the comparators. This makes the device easier to drive because it has con- stant capacitance and induces less slew rate distortion. An optional input buffer may be used. CLK, CLK (CLOCK INPUTS) The clock inputs are designed to be driven differentially with ECL levels. The clock may be driven single-ended since CLK is internally biased to –1.3 V. (See clock input circuit.) CLK may be left open, but a .01 µF bypass capaci- tor from CLK to AGND is recommended. NOTE: System performance may be degraded due to increased clock noise or jitter. MINV, LINV (OUTPUT LOGIC CONTROL) These are ECL-compatible digital controls for changing the output code from straight binary to two’s complement, etc. For more information, see table I. Both MINV and LINV are in the logic low (0) state when they are left open. The high state can be obtained by tying to AGND through a diode or 3.9 k Ω resistor. D0 TO D7 (DIGITAL OUTPUTS) The digital outputs can drive ECL levels into 50 Ω when pulled down to –2 V. When pulled down to –5.2 V, the out- puts can drive 150 Ω to 1 kΩ loads. VRBF, VR2, VRTF (REFERENCE INPUTS) There are two reference inputs and one external reference voltage tap. These are –2 V (VRBF), mid-tap (VR2), and AGND (VRTF). The reference pins can be driven as shown in figure 1. VR2 should be bypassed to AGND for further noise suppression. VRBF, VRBS, VR1, VR2, VR3, VRTF, VRTS REFERENCE INPUTS (PGA AND CERQUAD PACKAGES ONLY) These are five external reference voltage taps from –2 V (VRBF) to AGND (VRTF) that can be used to control integral linearity over temperature. The taps can be driven by op amps as shown in figure 2. These voltage level inputs can be bypassed to AGND for further noise suppression if so desired. VRB and VRT have force and sense pins for moni- toring the top and bottom voltage references. N/C All Not Connected pins should be tied to DGND on the left side of the package and to AGND on the right side of the package. DREAD – DATA READY; DRINV – DATA READY INVERSE (PGA AND CERQUAD PACKAGES ONLY) The data ready pin is a flag that goes high or low at the output when data is valid or ready to be received. It is es- sentially a delay line that accounts for the time neces- sary for information to be clocked through the SPT7725’s decoders and latches. This function is useful for interfac- ing with high-speed memory. Using the data ready output to latch the output data ensures minimum set-up and hold times. DRINV is a data ready inverse control pin. (See the timing diagram.) D8 – OVERRANGE (PGA AND CERQUAD PACKAGES ONLY) This is an overrange function. When the SPT7725 is in an overrange condition, D8 goes high and all data outputs go high as well. This makes it possible to include the SPT7725 into higher resolution systems. BINARY TWOs COMPLEMENT TRUE INVERTED TRUE INVERTED MINV=LINV=0 MINV=LINV=1 MINV=1; LINV=0 MINV=0; LINV=1 ANALOG INPUT VOLTAGE D8 D7_____D0 D7_____D0 D7_____D0 D7_____D0 –2 V + 1/2 LSB 0 00000000 11111111 10000000 01111111 00000001 11111110 10000001 01111110 –1.0 V 0 01111111 10000000 11111111 00000000 10000000 01111111 00000000 11111111 0 V – 1/2 LSB 0 11111111 00000000 01111111 10000000 11111110 00000001 01111110 10000001 ≥0 V 1 11111111 00000000 01111111 10000000 Table I – Output Coding |
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