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SPT7725BIJ Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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SPT7725BIJ Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 12 page 5 8/17/01 SPT7725 Figure 1 – Typical Interface Circuit 1 Analog Input Can Be Either Force Or Sense 127 2 1 Preamp Comparator 151 152 63 64 ECL Latches And Buffers VR2 VRTF LINV MINV 2 D1 D2 D3 D4 D5 D6 MSB D7 LSB D0 2 V (Digital) 50 W 50 W AGND .01 µF VEE 5.2 V L Clock Buffer + U1 5.2 V VEE AGND .01 µF .01 µF DGND .01 µF 255 256 VRBF CLK CLK Convert 100116 VIN VIN 256 To 8-Bit Encoder .01 µF 2 V (Analog) 2.2 µF Voltage Limiter *See below Analog Input Can Be Either Force Or Sense + U2 .01 µF VEE 2.2 2 V VRef 10 VEE Q1 (1N2907A) D1=D2=HP, 1N 5712 5.2 D1 D2 RS 49.9 Typical Voltage Limiter RT 128 GENERAL DESCRIPTION The SPT7725 is a fast monolithic 8-bit parallel flash A/D converter. The nominal conversion rate is 300 MSPS and the analog bandwidth is in excess of 200 MHz. A major ad- vance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators. (See block diagram.) This not only re- duces clock transient kickback to the input and reference ladder due to a low AC beta but also reduces the effect of the dynamic state of the input signal on the latching char- acteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it re- mains constant for varying input voltages and frequencies and, therefore, makes the part easier to drive than previ- ous flash converters. The SPT7725 incorporates a propri- etary decoding scheme that reduces metastable errors (sparkle codes or flyers) to a maximum of 1 LSB. The SPT7725 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. Every comparator also has a clock buffer to reduce differential delays and to improve signal-to- noise ratio. The output drive capability of the device can provide full ECL swings into 50 Ω loads. TYPICAL INTERFACE CIRCUIT The typical interface circuit is shown in figure 1. The SPT7725 is relatively easy to apply depending on the accuracy needed in the intended application. Wire-wrap may be employed with careful point-to-point ground con- nections if desired, but to achieve the best operation, a |
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