bq4802Y

bq4802LY

SLUS464C – AUGUST 2000 – REVISED JUNE 2002

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8

WRITE CYCLE TIMING DIAGRAMS

Address

Data-In Valid

High-Z

tWR1

CS

WE

DOUT

DIN

Data Undefined (see Note B)

tWZ

tOW

tDW

tWP

tAS

tCW

tAW

tWC

tDH1

NOTES: A. WE or CS must be held high during address transition.

B. Because I/O may be active (OE low) during the period, data input signals of opposite polarity to the outputs must be applied.

C. If OE is high, the I/O pins remain in a state of high impedance.

Figure 7. Write Cycle No. 1 – WE Controlled

Data-In Valid

High-Z

tWR2

DOUT

DIN

CS

WE

Address

Data Undefined (see Note B)

tWC

tAW

tCW

tWP

tDW

tDH2

tWZ

tAS

NOTES: A. WE or CS must be held high during address transition.

B. Because I/O may be active (OE low) during the period, data input signals of opposite polarity to the outputs must be applied.

C. If OE is high, the I/O pins remain in a state of high impedance.

D. Either tWR1 or tWR2 must be met.

E. Either tDH1 or tDH2 must be met.

Figure 8. Write Cycle No. 2 – CS Controlled