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AT89S8252-24PU Datasheet(PDF) 10 Page - ATMEL Corporation |
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AT89S8252-24PU Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 34 page  AT89S8252 10 the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transi- tion, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle. Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a l- to-0 transition at external input T2EX also causes the cur- rent value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus- trated in Figure 1. Figure 1. Timer 2 in Capture Mode Table 8. Timer 2 Operating Modes RCLK + TCLK CP/RL2 TR2 MODE 0 0 1 16-bit Auto-reload 0 1 1 16-bit Capture 1 X 1 Baud Rate Generator X X 0 (Off) OSC EXF2 T2EX PIN T2 PIN TR2 EXEN2 C/T2 = 0 C/T2 = 1 CONTROL CAPTURE OVERFLOW CONTROL TRANSITION DETECTOR TIMER 2 INTERRUPT ÷12 RCAP2L RCAP2H TH2 TL2 TF2 |
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