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MAX6803US29D3-T Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX6803US29D3-T Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 8 page 4-Pin, Low-Power µP Reset Circuits with Manual Reset 4 _______________________________________________________________________________________ Pin Description Applications Information Manual Reset Input Many µP-based products require manual reset capabil- ity, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic low on MR asserts reset. Reset remains asserted while MR is low, and for the reset active timeout period after MR returns high. MR has an internal 20k Ω pullup resistor, so it can be left unconnected if not used. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. Interfacing to µPs with Bidirectional Reset Pins Since the RESET output on the MAX6805 is open-drain, this device interfaces easily with µPs that have bidirec- tional reset pins, such as the Motorola 68HC11. Connecting the µP supervisor’s RESET output directly to the microcontroller’s (µC’s) RESET pin with a single pullup resistor allows either device to assert reset (Figure 1). Negative-Going VCC Transients In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, these devices are relatively immune to short-duration, negative-going VCC transients (glitches). The Typical Operating Characteristics show the Maximum Transient Duration vs. Reset Comparator Overdrive graph. The graph shows the maximum pulse width that a negative-going VCC transient may typically have without issuing a reset signal. As the amplitude of the transient increases, the maximum allowable pulse width decreases. Ensuring a Valid Reset Output down to VCC = 0 When VCC falls below 1V and approaches the minimum operating voltage of 0.7V, push/pull-structured reset sinking (or sourcing) capabilities decrease drastically. High-impedance CMOS-logic inputs connected to the RESET pin can drift to indeterminate voltages. This does not present a problem in most cases, since most VCC VCC GND MAX6805 RESET MR VCC GND RESET MOTOROLA 68HCXX µP 100k Ω Figure 1. Interfacing to µPs with Bidirectional Reset Pins PIN MAX6803 MAX6804 MAX6805 NAME FUNCTION 1 1 GND Ground — 2 RESET Active-Low Reset Output. RESET is asserted while VCC is below the reset threshold, or while MR is asserted. RESET remains asserted for a reset timeout period (tRP) after VCC rises above the reset threshold or MR is deasserted. RESET on the MAX6804 is push/pull. RESET on the MAX6805 is open-drain. Active-High Reset Output. RESET is asserted high while VCC is below the reset threshold or while MR is asserted, and RESET remains asserted for a reset timeout period (tRP) after VCC rises above the reset threshold or MR is deasserted. RESET on the MAX6803 is push/pull. RESET — 2 3 3 MR Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR is low, and for the reset timeout period (tRP) after MR goes high. Leave unconnected or connect to VCC if not used. Supply Voltage Input VCC 4 4 |
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