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LNBH26 Datasheet(PDF) 9 Page - STMicroelectronics |
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LNBH26 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 38 page  LNBH26 Application information (valid for each section A/B) Doc ID 022771 Rev 1 9/38 2.12 TMON: 22 kHz tone diagnostic The 22 kHz tone can be internally detected and monitored if one (or both) DETIN pin are connected to the LNB output bus (see Figure 7) through a decoupling capacitor. The tone diagnostic function is provided with the corresponding TMON I²C bit. If the 22 kHz tone amplitude and/or the tone frequency is out of the guaranteed limits (see Table 19), the corresponding TMON I²C bit is set to “1”. 2.13 TDET: 22 kHz tone detection When a 22 kHz tone presence is detected on one DETIN pin, the corresponding TDET I²C bit is set to “1”. 2.14 IMON: minimum output current diagnostic In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) each LNBH26 section is provided with a minimum output current flag by the corresponding IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than 12 mA (typ.). It is recommended to use the IMON function only with the 22 kHz tone transmission deactivated, otherwise the IMON bit could be set to “0” even if the output current is below the minimum current threshold. To activate the IMON diagnostic function, set to “1” the EN_IMON I²C bit in the DATA4 register. Be aware that as soon as the IMON function is activated by means of EN_IMON=1, the VOUT is immediately increased to 21 V (typ.) independently on the VSEL bit setting. This operation is applied in order to be sure that the LNBH26 output has the higher voltage present in the LNB bus. Do not use this function in an application environment where a 21 V voltage level is not supported by other peripherals connected to the LNB bus. 2.15 PDO: overcurrent detection on output pull-down stage When an overcurrent occurs on one section pull-down output stage due to an external voltage source greater than the LNBH26 nominal VOUT, and for a time longer than ISINK_TIME_OUT (10 ms typ.), the corresponding PDO I²C bit is set to “1”. This may happen due to an external voltage source presence on the LNB output (VOUT pin). For current threshold and deglitch time details, see Table 13. 2.16 Power-on I²C interface reset and undervoltage lockout The I²C interface built into the LNBH26 is automatically reset at power-on. As long as the VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor. |
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