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CBT3253ADB Datasheet(PDF) 5 Page - NXP Semiconductors |
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CBT3253ADB Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 15 page CBT3253A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 — 24 September 2013 5 of 15 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 9. Static characteristics [1] All typical values are measured at VCC =5V; Tamb =25 C. [2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. [3] Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. The lowest voltage of the two (A or B) terminals determines the ON resistance. 10. Dynamic characteristics [1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance). [2] tPLH and tPHL are the same as tpd. tPZL and tPZH are the same as ten. tPLZ and tPHZ are the same as tdis. Table 6. Static characteristics Tamb = 40 Cto+85 C. Symbol Parameter Conditions Min Typ[1] Max Unit VIK input clamping voltage VCC =4.5 V; II = 18 mA - - 1.2 V Vpass pass voltage VI =VCC = 5.0 V; IO = 100 A 3.6 3.9 4.2 V II input leakage current VCC =5.5 V; VI = GND or 5.5 V - - 1 A ICC supply current VCC =5.5 V; IO =0mA; VI =VCC or GND -- 3 A I CC additional supply current per input; VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND [2] -- 2.5 mA CI input capacitance control pins; VI = 3 V or 0 V -4.5 -pF Cio(off) off-state input/output capacitance A port; VO = 3 V or 0 V; nOE =VCC - 11.4 - pF B port; VO = 3 V or 0 V; nOE =VCC -3.8 -pF Cio(on) on-state input/output capacitance A port and B port - 18.6 - pF RON ON resistance VCC =4.5 V [3] VI =0V; II =64mA - 5 7 VI =0V; II =30mA - 5 7 VI = 2.4 V; II =15mA - 10 15 Table 7. Dynamic characteristics Tamb = 40 Cto+85 C; VCC = 4.5 V to 5.5 V; for test circuit, see Figure 6. Symbol Parameter Conditions Min Max Unit tpd propagation delay nA to nBn or nBn to nA; see Figure 4 [1][2] -0.25 ns Sn to nA; see Figure 4 [1][2] 1.2 6.2 ns ten enable time nOE to nA or nBn; see Figure 5 [2] 1.3 6.3 ns Sn to nBn; see Figure 5 [2] 1.4 6.4 ns tdis disable time nOE to nA or nBn; see Figure 5 [2] 1.1 7.2 ns Sn to nBn; see Figure 5 [2] 1.0 7 ns |
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