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PCA9554BS Datasheet(PDF) 10 Page - NXP Semiconductors |
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PCA9554BS Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 35 page PCA9554_9554A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 9 — 19 March 2013 10 of 35 NXP Semiconductors PCA9554; PCA9554A 8-bit I2C-bus and SMBus I/O port with interrupt 6.5 Device address 6.6 Bus transactions Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown in Figure 11 and Figure 12. Data is read from the PCA9554/PCA9554A registers using the Read mode as shown in Figure 13 and Figure 14. These devices do not implement an auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. Fig 9. PCA9554 device address Fig 10. PCA9554A device address 002aac494 0 1 0 0 A2 A1 A0 R/W fixed slave address hardware selectable 002aac495 0 1 1 1 A2 A1 A0 R/W fixed slave address hardware selectable Fig 11. Write to Output Port register 1 0 0 A2 A1 A0 0 A S0 START condition R/W acknowledge from slave 002aac472 A acknowledge from slave SCL SDA A write to port data out from port P tv(Q) 9 8 7 6 5 4 3 2 1 command byte acknowledge from slave data to port DATA 1 slave address 0000001 0 STOP condition data 1 valid Fig 12. Write to Configuration register or Polarity Inversion register 1 0 0 A2 A1 A0 0 A S0 START condition R/W acknowledge from slave 002aac473 A acknowledge from slave SCL SDA A data to register P 9 8 7 6 5 4 3 2 1 command byte acknowledge from slave data to register DATA slave address 000001 1/0 0 STOP condition |
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