TMS320DM369

www.ti.com

SPRT666 – APRIL 2013

TMS320DM369

Digital Media System-on-Chip (DMSoC)

1

TMS320DM369 Digital Media System-on-Chip (DMSoC)

1.1

Features

1

• Highlights

• ARM926EJ-S™ Core

– High-Performance Digital Media System-on-

– Support for 32-Bit and 16-Bit

Chip (DMSoC)

(Thumb® Mode) Instruction Sets

– 432-MHz ARM926EJ-S Clock Rate

– DSP Instruction Extensions and Single Cycle

MAC

– Three Video Image Co-processors

(Noise Filtering, CHDVICP, MJCP) Engines

– ARM® Jazelle® Technology

– Supports a Range of Encode, Decode, and

– Embedded ICE-RT Logic for Real-Time

Video Quality Operations

Debug

– Video Processing Subsystem

• ARM9 Memory Architecture

•

HW Face Detect Engine

– 16K-Byte Instruction Cache

•

Resize Engine from 1/16x to 8x

– 8K-Byte Data Cache

•

16-Bit Parallel AFE (Analog Front-End)

– 32K-Byte RAM

Interface Up to 120 MHz

– 16K-Byte ROM

•

4:2:2 (8-/16-bit) Interface

– Little Endian

•

8-/16-bit YCC and Up to 24-Bit RGB888

• Three Video Image Co-processors

Digital Output

(Noise Filtering, HDVICP, MJCP) Engines

•

3 DACs for HD Analog Video Output

– Support a Range of Encode and Decode

•

Hardware On-Screen Display (OSD)

Operations

– Capable of 1080p 30fps H.264 video

– H.264, MPEG4, MPEG2, MJPEG, JPEG,

processing

WMV9/VC1

– Peripherals include EMAC, USB 2.0 OTG,

– Noise Filtering Engine

DDR2/NAND, 5 SPIs, 2 UARTs, 2

• Video Processing Subsystem

MMC/SD/SDIO, Key Scan

– Front End Provides:

– 8 Different Boot Modes and Configurable

•

HW Face Detect Engine

Power-Saving Modes

•

Hardware IPIPE for Real-Time Image

– Pin-to-pin and software compatible with

Processing

DM365

–

Resize Engine

– Extended temperature (-40ºC to 85ºC)

–

Resize Images From 1/16x to 8x

available

–

Separate Horizontal/Vertical

– 3.3-V and 1.8-V I/O, 1.35-V Core

Control

– 338-Pin Ball Grid Array at 65nm Process

–

Two Simultaneous Output Paths

Technology

•

IPIPE Interface (IPIPEIF)

• High-Performance Digital Media System-on-

•

Image Sensor Interface (ISIF) and CMOS

Chip (DMSoC)

Imager Interface

– 432-MHz ARM926EJ-S Clock Rate

•

16-Bit Parallel AFE (Analog Front End)

– 4:2:2 (8-/16-Bit) Interface

Interface Up to 120 MHz

– Capable of 1080p 30fps H.264 video

•

Glueless Interface to Common Video

processing

Decoders

– Pin compatible with DM365 processors

•

BT.601/BT.656/BT.1120 Digital YCbCr

– Fully Software-Compatible With ARM9™

4:2:2 (8-/16-Bit) Interface

– Extended temperature available for 432-MHz

•

Histogram Module

device

•

Lens distortion correction module (LDC)

– Back End Provides:

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PRODUCTION DATA information is current as of publication date. Products conform to

Copyright © 2013, Texas Instruments Incorporated

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.