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DCS04S0A0S20NFA Datasheet(PDF) 10 Page - Delta Electronics, Inc. |
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DCS04S0A0S20NFA Datasheet(HTML) 10 Page - Delta Electronics, Inc. |
10 / 19 page DS_DCT04S0A0S03NFA_05292012 E-mail: DCDC@delta.com.tw http://www.deltaww.com/dcdc P10 TEST CONFIGURATIONS Figure 29: Input reflected-ripple test setup Vo GND 10uF tantalum 1uF ceramic SCOPE Resistive Load Note: Use a 10μF tantalum and 1μF capacitor. Scope measurement should be made using a BNC connector. Figure 30: Peak-peak output noise and startup transient measurement test setup. VI Vo GND Figure 31: Output voltage and efficiency measurement test setup Note: All measurements are taken at the module terminals. When the module is not soldered (via socket), place Kelvin connections at module terminals to avoid measurement errors due to contact resistance. % 100 ) ( Ii Vi Io Vo DESIGN CONSIDERATIONS Input Source Impedance To maintain low noise and ripple at the input voltage, it is critical to use low ESR capacitors at the input to the module. A highly inductive source can affect the stability of the module. An input capacitance must be placed close to the modules input pins to filter ripple current and ensure module stability in the presence of inductive traces that supply the input voltage to the module. |
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