DIGITAL INPUT TIMING REQUIREMENTS

TLV5630

TLV5631

TLV5632

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL OUTPUT

High-level digital output

2.6

V

voltage

Low-level digital output

0.4

V

voltage

5

10

ns

ANALOG OUTPUT DYNAMIC PERFORMANCE

Fast

1

3

Output settling time, full

(5)

µs

scale

Slow

3

7

Fast

0.5

1

Output settling time,

(6)

µs

code to code

Slow

1

2

Fast

4

10

SR

Slew rate

(7)

V/

µs

Slow

1

3

Glitch energy

4

nV-s

Channel crosstalk

90

dB

(5)

Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of

0x080 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.

(6)

Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one

count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.

(7)

Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

(8)

Code transition: TLV5630 - 0x7FF to 0x800, TLV5631 - 0x7FCto 0x800, TLV5632 - 0x7F0 to 0x800.

PARAMETER

MIN

TYP

MAX

UNIT

Setup time, FS low before next negative SCLK edge

8

ns

10

ns

of FS.

µC mode only

10

ns

DSP mode, setup time, SLCK low before FS low.

5

ns

LDAC duration low

10

ns

SCLK pulse duration high

16

ns

SCLK pulse duration low

16

ns

Setup time, FS low before first negative SCLK edge

8

ns

Setup time, data ready before SCLK falling edge

8

ns

Hold time, data held valid after SCLK falling edge

5

ns

FS duration high

10

ns

FS duration low

10

ns

See AC

Settling time

specs

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