SN65LVDS125

SN65LVDT125

SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004

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2

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

LOGIC DIAGRAM

1A

1B

1Y

1Z

1DE

2A

2B

2Y

2Z

2DE

3A

3B

3Y

3Z

3DE

4A

4B

4Y

4Z

4DE

4X4

MUX

8

S10 − S41

Integrated 110-

W Termination on LVDT Only