Electronic Components Datasheet Search |
|
AT45DB021E-MHN-T Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
|
AT45DB021E-MHN-T Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 68 page 7 AT45DB021E 8789E–DFLASH–10/2013 5. Read Commands By specifying the appropriate opcode, data can be read from the main memory or from the data buffer. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25., "Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3" on page 55 for diagrams detailing the clock cycle sequences for each mode. 5.1 Continuous Array Read (Legacy Command: E8h) By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read from memory to be performed without the need for additional address sequences. To perform a Continuous Array Read using the standard DataFlash page size (264-bytes), an opcode of E8h must be clocked into the device followed by three address bytes (which comprise the 19-bit page and byte address sequence) and four dummy bytes. The first 10 bits (PA9 - PA0) of the 19-bit address sequence specify which page of the main memory array to read and the last nine bits (BA8 - BA0) of the 19-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode E8h must be clocked into the device followed by three address bytes (A17 - A0) and four dummy bytes. The dummy bytes that follow the address bytes are needed to initialize the read operation. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO (Serial Output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses the data buffer and leaves the contents of the Buffer unchanged. Note: This command is not recommended for new designs. 5.2 Continuous Array Read (High Frequency Mode: 0Bh Opcode) This command can be used to read the main memory array sequentially at the highest possible operating clock frequency up to the maximum specified by fCAR1. To perform a Continuous Array Read using the standard DataFlash page size (264 bytes), the CS pin must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by three address bytes and one dummy byte. The first 10 bits (PA9 - PA0) of the 19-bit address sequence specify which page of the main memory array to read and the last nine bits (BA8 - BA0) of the 19-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size (256 bytes), the opcode 0Bh must be clocked into the device followed by three address bytes (A17 - A0) and one dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO pin. The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses the data buffer and leaves the contents of the Buffer unchanged. |
Similar Part No. - AT45DB021E-MHN-T |
|
Similar Description - AT45DB021E-MHN-T |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |