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ADS1274IPAPTG4 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS1274IPAPTG4 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 51 page  CLK t CPW t CLK t CPW t SD t SCLK t DIST t DOHD t SPW Bit23(MSB) Bit22 Bit21 t SPW t DOPD t CD t DS t MSBPD t DIHD · · · t CONV DRDY SCLK DOUT DIN ADS1274 ADS1278 SBAS367F – JUNE 2007 – REVISED FEBRUARY 2011 www.ti.com SPI FORMAT TIMING SPI FORMAT TIMING SPECIFICATION For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V, unless otherwise noted. SYMBOL PARAMETER MIN TYP MAX UNIT tCLK CLK period (1/fCLK) (1) 37 10,000 ns tCPW CLK positive or negative pulse width 15 ns tCONV Conversion period (1/fDATA) (2) 256 2560 tCLK tCD (3) Falling edge of CLK to falling edge of DRDY 22 ns tDS (3) Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 tCLK tMSBPD DRDY falling edge to DOUT MSB valid (propagation delay) 16 ns tSD (3) Falling edge of SCLK to rising edge of DRDY 18 ns tSCLK (4) SCLK period 1 tCLK tSPW SCLK positive or negative pulse width 0.4 tCLK tDOHD (3) (5) SCLK falling edge to new DOUT invalid (hold time) 10 ns 32 ns tDOPD (3) SCLK falling edge to new DOUT valid (propagation delay) 26 ns(6) tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns tDIHD (5) Old DIN valid to falling edge of SCLK (hold time) 6 ns (1) fCLK = 27MHz maximum. (2) Depends on MODE[1:0] and CLKDIV selection. See Table 8 (fCLK/fDATA). (3) Load on DRDY and DOUT = 20pF. (4) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. (5) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is > 4ns. (6) DOUT1, TDM mode, IOVDD = 3.15V to 3.45V, and DVDD = 1.7V to 1.9V. 8 Submit Documentation Feedback © 2007–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1274 ADS1278 |
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