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TPS70348PWPRG4 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS70348PWPRG4 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 46 page  TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 Detailed Description The TPS703xx low dropout regulator family provides dual regulated output voltages for DSP applications that require a high-performance power management solution. These devices provide fast transient response and high accuracy, while drawing low quiescent current. Programmable sequencing provides a power solution for DSPs without any external component requirements. This reduces the component cost and board space while increasing total system reliability. The TPS703xx family has an enable feature that puts the device into sleep mode, reducing the input current to 1 mA. Other features are the integrated SVS (power-on reset, RESET) and power good (PG1). These differential features monitor output voltages and provide logic output to the system, and provide a complete DSP power solution. The TPS703xx, unlike many other LDOs, features very low quiescent current that remains virtually constant even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/b). The TPS703xx uses a PMOS transistor to pass current. Because the gate of the PMOS is voltage driven, operating current is low and stable over the full load range. Pin Functions Enable (EN) The EN terminal is an input that enables or shuts down the device. If EN is at a logic high signal, the device is in shutdown mode. When EN goes to voltage low, then the device is enabled. Sequence (SEQ) The SEQ terminal is an input that programs the output voltage (VOUT1 or VOUT2) that turns on first. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. If VOUT2 is pulled below 83% (that is, goes to an overload) VOUT1 is turned off. This terminal has a 6 mA pull-up current to VIN1. Pulling the SEQ terminal low reverses the power-up order and VOUT1 turns on first. For detailed timing diagrams, see Figure 33 through Figure 39. Power-Good (PG1) The PG1 terminal is an open drain, active high output terminal that indicates the status of the VOUT1 regulator. When VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. PG1 goes to a low impedance state when VOUT1 is pulled below 95% (that is, goes to an overload condition) of its regulated voltage. The open drain output of the PG1 terminal requires a pull-up resistor. Manual Reset Pins (MR1 and MR2) MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled to logic low, a POR (RESET) occurs. These terminals have a 6mA pull-up current to VIN1. It is recommended that these pins be pulled high to VIN when they are not used.. Sense (VSENSE1 and VSENSE2) The sense terminals of fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, the sense terminals connect to high-impedance wide-bandwidth amplifiers through resistor-divider networks and noise pickup feeds through to the regulator output. It is essential to route the sense connections in such a way to minimize or avoid noise pickup. Adding RC networks between the VSENSE terminals and VOUT terminals to filter noise is not recommended because these networks can cause the regulators to oscillate. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 |
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