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MSP430F6775IPEUR Datasheet(PDF) 7 Page - Texas Instruments

Part # MSP430F6775IPEUR
Description  POLYPHASE METERING SoCs
Download  157 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP430F6775IPEUR Datasheet(HTML) 7 Page - Texas Instruments

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PEU PACKAGE
1
XIN
2
XOUT
3
AUXVCC3
4
RTCCAP1
5
RTCCAP0
6
P1.5/SMCLK/CB0/A5
7
P1.4/MCLK/CB1/A4
8
P1.3/ADC10CLK/A3
9
P1.2/ACLK/A2
10
P1.1/TA2.1/VeREF+/A1
11
P1.0/TA1.1/VeREF-/A0
12
P2.4/PM_TA2.0
13
P2.5/PM_UCB0SOMI/PM_UCB0SCL
14
P2.6/PM_UCB0SIMO/PM_UCB0SDA
15
P2.7/PM_UCB0CLK
16
P3.0/PM_UCA0RXD/PM_UCA0SOMI
17
P3.1/PM_UCA0TXD/PM_UCA0SIMO
18
P3.2/PM_UCA0CLK
19
P3.3/PM_UCA1CLK
20
P3.4/PM_UCA1RXD/PM_UCA1SOMI
21
P3.5/PM_UCA1TXD/PM_UCA1SIMO
22
COM0
23
COM1
24
P1.6/COM2
25
P1.7/COM3
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
78
P9.7/S9
79
P10.0/S8
80
P10.1/S7
81
P10.2/S6
82
P10.3/S5
83
P10.4/S4
84
P10.5/S3
85
P10.6/S2
86
P10.7/S1
87
P11.0/S0
88
P11.1/TA3.1/CB3
89
P11.2/TA1.1
90
P11.3/TA2.1
91
P11.4/CBOUT
92
P11.5/TACLK/RTCCLK
93
P2.0/PM_TA0.0/BSL_TX
94
P2.1/PM_TA0.1/BSL_RX
95
P2.2/PM_TA0.2
96
P2.3/PM_TA1.0
97
TEST/SBWTCK
98
PJ.0/TDO
99
PJ.1/TDI/TCLK
100
PJ.2/TMS
101
PJ.3/TCK
102
RST/NMI/SBWTDIO
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
26
P5.0/COM4
27
P5.1/COM5
28
P5.2/COM6
29
P5.3/COM7
30
LCDCAP/R33
31
P5.4/SDCLK/R23
32
P5.5/SD0DIO/LCDREF/R13
33
P5.6/SD1DIO/R03
34
P5.7/SD2DIO/CB2
35
P6.0/SD3DIO
36
P3.6/PM_UCA2RXD/PM_UCA2SOMI
37
P3.7/PM_UCA2TXD/PM_UCA2SIMO
38
P4.0/PM_UCA2CLK
64
103
65
P8.4/S20
66
P8.5/S19
67
P8.6/S18
68
P8.7/S17
69
VDSYS2
70
DVSS2
71
P9.0/S16
72
P9.1/S15
73
P9.2/S14
74
P9.3/S13
75
P9.4/S12
76
P9.5/S11
77
P9.6/S10
ECCN 5E002 TSPA - Technology / Software Publicly Available
MSP430F677x
MSP430F676x
MSP430F674x
www.ti.com
SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013
Pin Designation, MSP430F677xIPEU
A.
The secondary digital functions on Ports P2, P3 and P4 are fully mappable. The pin designation shows only the
default mapping. See Table 16 for details.
B.
The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper
device operation.
C.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.
Copyright © 2012–2013, Texas Instruments Incorporated
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