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PCM1725UG4 Datasheet(PDF) 6 Page - Texas Instruments |
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PCM1725UG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 14 page ® 6 PCM1725 FIGURE 1. “Normal” Data Input Timing. FIGURE 2. “I2S” Data Input Timing. LRCKIN BCKIN DIN 1.4V 1.4V 1.4V t BCH t BCL t LB t BL t DS BCKIN Pulse Cycle Time BCKIN Pulse Width High BCKIN Pulse Width Low BCKIN Rising Edge to LRCIN Edge LRCIN Edge to BCKIN Rising Edge DIN Set-up Time DIN Hold Time : t BCY : t BCH : t BCL : t BL : t LB : t DS : t DH : 100ns (min) : 50ns (min) : 50ns (min) : 30ns (min) : 30ns (min) : 30ns (min) : 30ns (min) t DH t BCY FIGURE 3. Audio Data Input Timing. SYSTEM CLOCK The system clock for PCM1725 must be either 256fS or 384fS, where fS is the audio sampling frequency (LRCIN), typically 32kHz, 44.1kHz or 48kHz. The system clock is used to operate the digital filter and the noise shaper. The system clock input (SCKI) is at pin 14. Timing conditions for SCKI are shown in Figure 4. System Clock Pulse Width High tSCKIH 13ns (min) System Clock Pulse Width Low tSCKIL 13ns (min) t SCKIH SCKI t SCKIL 2.0V 0.8V FIGURE 4. System Clock Timing Requirements. 14 15 16 1 2 3 14 15 1/fs L_ch R_ch MSB LSB 16 LRCIN (pin 1) BCKIN (pin 3) AUDIO DATA WORD = 16-BIT DIN (pin 2) 1 2 3 14 15 MSB LSB 16 1 2 3 14 15 1/fs L_ch R_ch MSB LSB 16 LRCIN (pin 1) BCKIN (pin 3) AUDIO DATA WORD = 16-BIT DIN (pin 2) 1 2 3 14 15 MSB LSB 16 2 1 Not Recommended For New Designs |
Similar Part No. - PCM1725UG4 |
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Similar Description - PCM1725UG4 |
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