®

7

PCM1725

PCM1725 has a system clock detection circuit which auto-

matically detects the frequency, either 256f

system clock should be synchronized with LRCIN (pin 1),

but PCM1725 can compensate for phase differences. If the

phase difference between LRCIN and system clock is greater

than

±6 bit clocks (BCKIN), the synchronization is per-

formed automatically. The analog outputs are forced to a

bipolar zero state (V

tion. Table I shows the typical system clock frequency

inputs for the PCM1725.

SYSTEM CLOCK

FREQUENCY (MHz)

32kHz

8.192

12.288

44.1kHz

11.2896

16.9340

48kHz

12.288

18.432

SAMPLING

RATE (LRCIN)

TABLE I. System Clock Frequencies vs Sampling Rate.

TYPICAL CONNECTION DIAGRAM

Figure 5 illustrates the typical connection diagram for

PCM1725 used in a stand-alone application.

INPUT DATA FORMAT

PCM1725 can accept input data in either normal (MSB-first,

LOW, normal data format is selected; a HIGH on pin 13

FORMAT

0

Normal Format (MSB-first, right-justified)

TABLE II. Input Format Selection.

FIGURE 6. Internal Power-On Reset Timing.

DIN

BCKIN

LRCIN

2

3

1

13

12

FORMAT

DM

SCKI

9

5

78

6

14

PCM

Audio Data

Processor

256f

GND

Mode Control

Lch Analog Out

+5V Analog

Rch Analog Out

V

CC

V

V

CAP

PCM1725

+

10µF

Post

LPF

Post

LPF

FIGURE 5. Typical Connection Diagram.

RESET

PCM1725 has an internal power-on reset circuit. The internal

power-on reset initializes (resets) when the supply voltage

During the initialization period, the outputs of the DAC are

illustrates the power-on reset and reset-pin reset timing.

DE-EMPHASIS CONTROL

Pin 12 (DM) enables PCM1725’s de-emphasis function. De-

emphasis operates only at 44.1kHz.

DM

0

DEM OFF

1

DEM ON (44.1kHz)

TABLE III. De-Emphasis Control Selection.

1024 system (= SCKI) clocks

Reset

Reset Removal

2.6V

2.2V

1.8V

V

CC

Internal Reset

SCKI Clock

Not Recommended For New Designs