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MSP430F6767IPZ Datasheet(PDF) 9 Page - Texas Instruments |
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MSP430F6767IPZ Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 157 page  PZ PACKAGE 1 SD0P0 2 SD0N0 3 SD1P0 4 SD1N0 5 SD2P0 6 SD2N0 7 SD3P0 8 SD3N0 9 VASYS2 10 AVSS2 11 VREF 12 SD4P0 13 SD4N0 14 SD5P0 15 SD5N0 16 SD6P0 17 SD6N0 18 AVSS1 19 AVCC 20 VASYS1 21 AUXVCC2 22 AUXVCC1 23 VDSYS1 24 DVCC 25 DVSS1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 P3.0/PM_UCA0RXD/PM_UCA0SOMI 52 P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39 53 P3.2/PM_UCA0CLK/S38 54 P3.3/PM_UCA1CLK/S37 55 P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36 56 P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35 57 P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34 58 P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33 59 P4.0/PM_UCA2CLK/S32 60 P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31 61 P4.4/PM_UCA3TXD/PM_UCA3SIMO/S30 62 P4.3/PM_UCA3CLK/S29 63 P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28 64 P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27 65 P4.6/PM_UCB1CLK/S26 66 P4.7/PM_TA3.0/S25 67 P5.0/SDCLK/S24 68 P5.1/SD0DIO/S23 69 P5.2/SD1DIO/S22 70 P5.3/SD2DIO/S21 71 P5.4/SD3DIO/S20 72 P5.5/SD4DIO/S19 73 P5.6/SD5DIO/S18 74 P5.7/SD6DIO/S17 75 VDSYS2 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x MSP430F676x MSP430F674x www.ti.com SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013 Pin Designation, MSP430F677xIPZ D. The secondary digital functions on Ports P2, P3 and P4 are fully mappable. The pin designation shows only the default mapping. See Table 16 for details. E. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper device operation. F. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 |
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