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SWITCHING CHARACTERISTICS

SN65LVDS100, SN65LVDT100

SN65LVDS101, SN65LVDT101

SLLS516C – AUGUST 2002 – REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

SN65LVDS100 and SN65LVDT100 OUTPUT CHARACTERISTICS (see Figure 1)

Differential output voltage magnitude

247

340

454

See Figure 2

mV

Change in differential output voltage magni-

∆|V

–50

50

tude between logic states

Steady-state common-mode output voltage

1.125

1.375

V

Change in steady-state common-mode output

∆V

OC(SS)

See Figure 3

–50

50

mV

voltage between logic states

Peak-to-peak common-mode output voltage

50

150

mV

Short-circuit output current

–24

24

mA

Differential short-circuit output current

–12

12

mA

SN65LVDS101 and SN65LVDT101 OUTPUT CHARACTERISTICS (see Figure 1)

50

Ω to V

V

High-level output voltage

2055

2280

2405

mV

50

Ω to V

V

Low-level output voltage

1475

1690

1775

mV

Differential output voltage magnitude

50-

Ω load to V

475

575

750

mV

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MAX

UNIT

'LVDx100

300

470

800

Propagation delay time,

ps

low-to-high-level output

'LVDx101

400

630

900

'LVDx100

300

470

800

Propagation delay time,

ps

high-to-low-level output

'LVDx100

See Figure 5

400

630

900

Differential output signal rise time (20%–80%)

220

ps

Differential output signal fall time (20%–80%)

220

ps

(2)

5

50

ps

(3)

100

ps

(4)

1

3.7

ps

1 GHz 50% duty cycle square wave input,

(5)

6

23

ps

28

65

ps

(6)

17

48

ps

(1)

All typical values are at 25

°C and with a 3.3 V supply.

(2)

(3)

devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(4)

Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 1000,000 cycles.

(5)

Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle

pairs.

(6)

Deterministic jitter is the sum of pattern-dependent jitter and pulse-width distortion.

4