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BQ24071 Datasheet(PDF) 6 Page - Texas Instruments |
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BQ24071 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 31 page bq24070 bq24071 SLUS694F – MARCH 2006 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MODE INPUT Falling Hi →Low; 280 K ± 10% applied when VIL Low-level input voltage 0.975 1 1.025 V low. VIH High-level input voltage Input RMode sets external hysteresis VIL + .01 VIL + .024 V IIL Low-level input current, Mode –1 μA TIMERS K(TMR) Timer set factor t(CHG) = K(TMR) × R(TMR) 0.313 0.360 0.414 s/ Ω R(TMR) (10) External resistor limits 30 100 k Ω 0.09 × t(PRECHG) Precharge timer 0.10 × t(CHG) 0.11 × t(CHG) s t(CHG) Timer fault recovery pullup from I(FAULT) 1 k Ω OUT to BAT CHARGER SLEEP THRESHOLDS (PG THRESHOLDS, LOW → POWER GOOD) VVCC ≤ V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG), V(SLPENT) (11) Sleep-mode entry threshold VI(BAT) No t(BOOT-UP) delay +125 mV V VVCC ≥ V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG), V(SLPEXIT) (11) Sleep-mode exit threshold VI(BAT) No t(BOOT-UP) delay +190 mV R(TMR) = 50 kΩ, t(DEGL) De-glitch time for sleep mode(12) V(IN) decreasing below threshold, 100-ns fall 22.5 ms time, 10-mv overdrive START-UP CONTROL BOOT-UP On the first application of input with Mode t(BOOT-UP) Boot-up time 120 150 180 ms Low SWITCHING POWER SOURCE TIMING When input applied. Measure from: Switching power source from input [PG: Lo → Hi to I(IN) > 5 mA], tSW-BAT 50 μs to battery I(OUT) = 100 mA, RTRM = 50 K THERMAL SHUTDOWN REGULATION(13) T(SHTDWN) Temperature trip TJ (Q1 and Q3 only) 155 Thermal hysteresis TJ (Q1 and Q3 only) 30 °C TJ(REG) Temperature regulation limit TJ (Q2) 115 135 UVLO V(UVLO) Undervoltage lockout Decreasing VCC 2.45 2.50 2.65 V Hysteresis 27 mV VREF OUTPUT Active only if AC or USB is present, VO(VREF) Output regulation voltage 3.3 V VI(OUT) ≥ VO(VREF) + (IO(VREF) × RDS(on)) Regulation accuracy(14) –5% 5% IO(VREF) Output current 20 mA RDS(on) On resistance OUT to VREF 50 Ω C(OUT) (15) Output capacitance 1 μF (10) To disable the fast-charge safety timer and charge termination, tie TMR to the VREF pin. Tying the TMR pin high changes the timing resistor from the external value to an internal 50 k Ω ±25%, which can add an additional tolerance to any timed specification. The TMR pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum time extension of 2.5 V ÷ 0.8 V × 100 = 310%. (11) The IC is considered in sleep mode when IN is absent (PG = OPEN DRAIN). (12) Does not declare sleep mode until after the de-glitch time and implement the needed power transfer immediately according to the switching specification. (13) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically does not cause a thermal shutdown (input FETs turning off) by itself. (14) In standby mode (CE low) the accuracy is ±10%. (15) VREF output capacitor not required, but one with a value of 0.1 μF is recommended. 6 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): bq24070 bq24071 |
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