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SIC413 Datasheet(PDF) 10 Page - Vishay Siliconix

Part # SIC413
Description  microBUCKTM SiC413 4-A, 26-V Integrated Synchronous Buck Regulator
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Manufacturer  VISHAY [Vishay Siliconix]
Direct Link  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

SIC413 Datasheet(HTML) 10 Page - Vishay Siliconix

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10
Document Number: 69057
S09-2250-Rev. D, 26-Oct-09
Vishay Siliconix
SiC413
output voltage is fed back at the FB pin. This feedback signal
is summed with a precision voltage reference through a high
bandwidth transconductance amplifier, often referred to as
the error amplifier. This summation creates an error signal
that is proportional to the difference between the actual
output voltage and the desired output voltage, which is
achieved when the voltage at the center tap of the feedback
resistor divider is equal to the voltage reference. The error
signal is present at the COMP pin, which is the output of the
error amplifier.
The error amplifier in the SiC413CB has a high loop gain and
a 2.5 MHz Gain Bandwidth Product. It is designed this way
to provide fast transient response in applications such as
DRAM memory arrays in Graphics Cards. This lets the
control loop quickly respond to any deviation of the output
voltage. It also makes the SiC413CB more sensitive to noise
on the FB pin. It is recommended to add resistor R3 at 20 k
Ω
to help isolate the error amplifier from noise on the FB pin
and give the designer the full benefit of the fast response
time the SiC413CB can deliver.
Under normal operation the output of the error signal varies
between 1.0 V and 2.0 V. This corresponds to the peak to
peak amplitude of the saw-tooth wave form generated by the
oscillator at the input to the PWM comparator. The PWM
comparator drives the logic that controls the MOSFET gate
drivers. These drivers control the turn on and turn off of the
high- and low-side MOSFETs. As the error signal varies the
PWM duty cycle is adjusted up and down to counteract the
error. This interaction is normal load modulation and can be
seen in a slight jitter on the trailing edge of the PWM signal.
The resulting PWM signal at the VSW switching node is
integrated by the LC filter to deliver the desired DC output
voltage.
Very low steady state duty cycles occur when the desired
output is much smaller than the input (i.e. 24 V input to 1.2 V
output). In this case, the error signal will be closer to 1 V.
Very high duty cycles occur when the desired output is closer
to the input (i.e. 5 V input to 3.3 V output). In this case, the
error signal is closer to 2 V. As can be seen, in these cases
the error signal may have limited headroom for control under
severe load transient conditions. This can result an
asymmetrical transient response characteristic and slightly
longer regulation recovery times for either the load
acquisition or load shedding.
Open Loop Transfer Function
The following discussion derives the equations for the open
loop transfer function. The technique for selecting the poles
and zeros for optimized loop stability is then presented.
For
this
analysis
we
are
considering
the
LC filter
approximation given in Figure 4 and are not considering the
impedance of the load. However, most output impedances
can be modeled using the lumped circuit approximation
shown in Figure 4. One exception is the use of a
π filter with
a roll off frequency that is inside the loop bandwidth. In this
case, derivation of the transfer function that includes the
phase and gain effects of this filter is important. In some
cases,
π filters can reduce gain margin and cause marginal
stability if not considered thoroughly.
The loop gain transfer function is broken into four blocks,
each representing a different part of the buck converter. The
four blocks and their frequency domain equations are as
follows:
Block 1 - GLC: Output LC filter consisting of L1, C4, C5 and
R6
Block 2 - GSP: Output voltage sampling network composed
of C1, R1 and R2
Block 3 - GPWM: PWM modulation gain that equals to
VIN/ΔVOSC, where ΔVOSC = saw tooth peak to peak voltage
Block 4 - GCOMP: Amplifier compensator with components of
C2, C3, R4, R5 and the amplifier gain gM, which is a function
of frequency.
Resistor R4 value should be very large compared to R5.
The purpose of R4 is to eliminate non-monotonic output
behavior during rapidly pulsed off-then-on line transients. R4
provides a fast discharge path for C3 and resets the error
signal at COMP to zero before the line input pulses back on.
Ideally, R4 can be ignored for the purposes of the loop
transfer function.
Ignoring R4 gives the following simplified transfer function for
Block 4.
The overall open loop transfer function for this system, GOL,
is then the product of the four transfer functions derived for
each block.
Converting to the logarithm form we have
SR6 • C5 + 1
2
3
=
L1 • (C4 + C5) + SR6 • C5 + 1
R6 • C4 • C5 • L1 + S
S
G
LC
1
1
R1 + R2
R1 • R2
S+
R1 • C1
S+
G
SP
• C1
=
OSC
IN
PWM
V
G
ΔV
=
1
)
1
1
1
1
1
2
R4 • R5 • C2 • C3
R5 • C3
R4 • C3
R5 • C2
S
R5 • C2
S +
C3
g
G
M
COMP
+
+
+
+ S (
=
1
1
C2 + C3
C2 • C3
R5 •
S+
R5 • C2
S+
SC3
g
G
M
COMP
=
GOL = GLC • GSP • GPWM • GCOMP
GOL (dB) = G LC (dB) + GSP(dB) + GPWM (dB) + G COMP (dB)


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