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DAC8043AEPZ3 Datasheet(PDF) 4 Page - Analog Devices |
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DAC8043AEPZ3 Datasheet(HTML) 4 Page - Analog Devices |
4 / 8 page REV. B DAC8043A –4– SRI CLK LD SRI CLK LD FS ZS VOUT DATA LOADED MSB(D11) FIRST DAC REGISTER LOAD D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D0 D7 tLD1 tDS tDH tCL tCH tLD tS 1 LSB ERROR BAND Dxx tASB Figure 2. Timing Diagram Table I. Control-Logic Truth Table CLK LD Serial Shift Register Function DAC Register Function u H Shift-Register-Data Advanced One Bit Latched H or L L No Effect Updated with Current Shift Register Contents L u No Effect Latched All 12 Bits NOTES u positive logic transition. The DAC Register LD input is level-sensitive. Any time LD is logic-low data in the serial register will directly control the switches in the R-2R DAC ladder. TOTAL UNADJUSTED ERROR – LSB 15 20 0 –1.0 1.0 10 30 –0.5 0.0 0.5 SS = 200 UNITS TA = 25 C VDD = 5V VREF = 10V 25 5 35 Figure 3. Total Unadjusted Error Histogram Typical Performance Characteristics FULL SCALE TEMPCO – ppm/ C 30 20 0 0 10 40 50 SS = 200 UNITS TA = –40 C TO +85 C VDD = 5V VREF = 10V 12 Figure 4. Full-Scale Output Tempco Histogram |
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