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DAC8412BT-883C Datasheet(PDF) 8 Page - Analog Devices |
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DAC8412BT-883C Datasheet(HTML) 8 Page - Analog Devices |
8 / 20 page DAC8412/DAC8413 Data Sheet Rev. G | Page 8 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VREFH 1 VOUTB 2 VOUTA 3 VSS 4 VREFL 28 VOUTC 27 VOUTD 26 VDD 25 DGND 5 RESET 6 LDAC 7 VLOGIC 24 CS 23 A0 22 DB0 (LSB) 8 A1 21 DB1 9 R/W 20 DB2 10 DB11 (MSB) 19 DB3 11 DB10 18 DB4 12 DB9 17 DB5 13 DB8 16 DB6 14 DB7 15 DAC8412/ DAC8413 TOP VIEW (Not to Scale) 128 27 26 2 3 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 DGND RESET LDAC DB0 (LSB) DB1 DB2 DB3 VDD VLOGIC CS A0 A1 R/W DB11 (MSB) PIN 1 INDENTFIER 12 13 14 15 16 17 18 DAC8412/ DAC8413 TOP VIEW (Not to Scale) DAC8412/ DAC8413 TOP VIEW (Not to Scale) 5 DGND 6 RESET 7 LDAC 8 DB0 (LSB) 9 DB1 10 DB2 11 DB3 25 VDD 24 VLOGIC 23 CS 22 A0 21 A1 20 R/W 19 DB11 (MSB) 26 27 28 1 2 3 4 18 17 16 15 14 13 12 Figure 7. PDIP/CERDIP Figure 8. PLCC Figure 9. LCC Table 5. Pin Function Descriptions Pin Number Mnemonic Description 1 VREFH High-Side DAC Reference Input. 2 VOUTB DAC B Output. 3 VOUTA DAC A Output. 4 VSS Lower Rail Power Supply. 5 DGND Digital Ground. 6 RESET Reset Input and Output Registers to all 0s, Enabled at Active Low. 7 LDAC Load Data to DAC, Enabled at Active Low. 8 DB0 Data Bit 0, LSB. 9 DB1 Data Bit 1. 10 DB2 Data Bit 2. 11 DB3 Data Bit 3. 12 DB4 Data Bit 4. 13 DB5 Data Bit 5. 14 DB6 Data Bit 6. 15 DB7 Data Bit 7. 16 DB8 Data Bit 8. 17 DB9 Data Bit 9. 18 DB10 Data Bit 10. 19 DB11 Data Bit 11, MSB. 20 R/W Active Low to Write Data to DAC. Active high to readback previous data at data bit pins with VLOGIC connected to 5 V. 21 A1 Address Bit 1. 22 A0 Address Bit 0. 23 CS Chip Select, Enabled at Active Low. 24 VLOGIC Voltage Supply for Readback Function. Can be open circuit if not used. 25 VDD Upper Rail Power Supply. 26 VOUTD DAC D Output. 27 VOUTC DAC C Output. 28 VREFL Low-Side DAC Reference Input. |
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