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EVAL-ADuC7023QSPZ2 Datasheet(PDF) 11 Page - Analog Devices |
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EVAL-ADuC7023QSPZ2 Datasheet(HTML) 11 Page - Analog Devices |
11 / 96 page Data Sheet ADuC7023 | Page 11 of 96 Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit t SS SS to SCLK edge 200 ns tSL SCLK low pulse width1 (SPIDIV + 1) × tUCLK ns tSH SCLK high pulse width1 (SPIDIV + 1) × tUCLK ns tDAV Data output valid after SCLK edge 25 ns tDSU Data input setup time before SCLK edge1 1 × tUCLK ns tDHD Data input hold time after SCLK edge1 2 × tUCLK ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SCLK rise time 5 12.5 ns tSF SCLK fall time 5 12.5 ns tSFS SS high after SCLK edge 0 ns 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. MOSI MISO SCLK (POLARITY = 0) SCLK (POLARITY = 1) tSF tSFS tSR tSL tDAV tSH tDF tDR tDSU tDHD SS MSB BIT 6 TO BIT 1 LSB MSB IN BIT 6 TO BIT 1 LSB IN tSS Figure 5. SPI Slave Mode Timing (Phase Mode = 1) Rev. E |
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