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ADP7105 Datasheet(PDF) 5 Page - Analog Devices |
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ADP7105 Datasheet(HTML) 5 Page - Analog Devices |
5 / 28 page Data Sheet ADP7105 Rev. 0 | Page 5 of 28 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating VIN to GND −0.3 V to +22 V VOUT to GND −0.3 V to +20 V EN/UVLO to GND −0.3 V to VIN PG to GND −0.3 V to VIN SENSE/ADJ to GND −0.3 V to VOUT SS to GND −0.3 V to +3.6 V Storage Temperature Range −65°C to +150°C Operating Junction Temperature Range −40°C to +125°C Soldering Conditions JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP7105 can be damaged when the junction temperature (TJ) limit is exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor printed circuit board (PCB) thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θJA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD × θJA) Junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θJA may vary, depending on PCB material, layout, and environmental conditions. The specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit board. See JEDEC JESD51-7 and JESD51-9 for detailed information on the board construction. For additional information, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), available at www.analog.com. ΨJB is the junction-to-board thermal characterization parameter with units of °C/W. The package ΨJB is based on modeling and calculation using a 4-layer board. JEDEC JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than through a single path as in thermal resistance, θJB. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make ΨJB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD × ΨJB) See JESD51-8 and JESD51-12 for more detailed information about ΨJB. THERMAL RESISTANCE θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. θJC is a parameter for surface-mount packages with top mounted heat sinks. θJC is presented here for reference only. Table 4. Thermal Resistance Package Type θJA θJC ΨJB Unit 8-Lead LFCSP 40.1 27.1 17.2 °C/W 8-Lead SOIC 48.5 58.4 31.3 °C/W ESD CAUTION |
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