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AD974BR Datasheet(PDF) 9 Page - Analog Devices |
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AD974BR Datasheet(HTML) 9 Page - Analog Devices |
9 / 20 page REV. A AD974 –9– EXTERNAL DISCONTINUOUS CLOCK DATA READ DURING CONVERSION WITH NO SYNC OUTPUT GENERATED Figure 5 illustrates the method by which data from conversion “n-1” can be read during conversion “n” while using a discon- tinuous external clock, without the generation of a SYNC out- put. After a conversion is initiated, indicated by BUSY going low, the result of the previous conversion can be read while CS is low and R/ C is high. In this mode CS can be tied low. The MSB will be valid on the 1st falling edge and the 2nd rising edge of DATACLK. The LSB will be valid on the 16th falling edge and the 17th rising edge of DATACLK. A minimum of 16 clock pulses are required for DATACLK if the receiving device will be latching data on the falling edge of DATACLK. A minimum of 17 clock pulses are required for DATACLK if the receiving device will be latching data on the rising edge of DATACLK. In this mode the data should be clocked out during the first half of BUSY so not to degrade conversion performance. This re- quires use of a 10 MHz DATACLK or greater, with data being read out as soon as the conversion process begins. EXTERNAL DISCONTINUOUS CLOCK DATA READ AFTER CONVERSION WITH SYNC OUTPUT GENERATED Figure 6 illustrates the method by which data from conver- sion “n” can be read after the conversion is complete using a discontinuous external clock, with the generation of a SYNC output. What permits the generation of a SYNC output is a transition of DATACLK while either CS is high or while both CS and R/C are low. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is Low and R/C is high. In this mode CS can be tied low. In Figure 6 clock pulse #0 is used to enable the gen- eration of a SYNC pulse. The SYNC pulse is actually clocked out approximately 40 ns after the rising edge of clock pulse #1. The SYNC pulse will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. The MSB will be valid on the falling edge of clock pulse #2 and the rising edge of clock pulse #3. The LSB will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. The advan- tage of this method of reading data is that it is not being clocked out during a conversion and therefore conversion performance is not degraded. When reading data after the conversion is complete, with the highest frequency permitted for DATACLK (15.15 MHz), the maximum possible throughput is approximately 195 kHz and not the rated 200 kHz. EXT DATACLK R/ C BUSY SYNC DATA 0 BIT 15 (MSB) BIT 14 t12 t13 t14 1 2 15 16 t15 t1 t20 t2 t21 t18 t18 BIT 0 (LSB) t22 Figure 5. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low) EXT DATACLK R/ C BUSY SYNC DATA 0 t12 12 3 18 t13 t14 417 t15 t15 t15 t2 t17 t12 t18 t18 BIT 15 (MSB) BIT 14 BIT 0 (LSB) Figure 6. Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low) |
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